RE: [PATCH] ARM: dts: aspeed: anacapa: name EDSFF and thermtrip SGPIO lines

AMD General

Hi Andrew,

Thanks for the review.

I agree that the original commit message was too vague, especially since these GPIO line names are visible to userspace.

There is no new board revision or underlying hardware change involved. This is a naming correction for the existing Anacapa hardware design.

I will remove the "legacy or unused" wording. The previous names do not match the actual Anacapa usage: some lines were named as CPU-related signals but are used for EDSFF power-good monitoring, and the thermtrip lines used raw active-low signal names while userspace monitors the asserted condition.

Changing these names is appropriate because the userspace monitoring configuration is based on the platform signal names. Keeping the old names would make the DTS inconsistent with the hardware design and userspace configuration.

I will send a v2 with the exact old-to-new mappings and a more precise explanation in the commit message.

Best regards,
Rex Fu
BMC Engineer  |  AMD
Data Center Platform Engineering Group
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-----Original Message-----
From: Andrew Jeffery <[email protected]>
Sent: Monday, May 18, 2026 2:48 PM
To: Fu, Rex <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Conor Dooley <[email protected]>; Joel Stanley <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH] ARM: dts: aspeed: anacapa: name EDSFF and thermtrip SGPIO lines

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Hello Rex,

On Thu, 2026-04-30 at 13:44 +0800, Rex Fu via B4 Relay wrote:
> From: Rex Fu <[email protected]>
>
> Name the Anacapa SGPIO lines used for EDSFF power-good and thermtrip
> assertion signals.
>
> The affected lines replace legacy
>

Which are legacy?

>  or unused
>

Which are unused?

> CPU-related names with the
> platform signal names used by userspace monitoring.

This is the kind of change that has the potential to break old userspace. Why is it appropriate? I'd like a more precise discussion in the commit message.

Was there some other underlying change (e.g. a new revision of the platform design)?

Andrew

>
> Signed-off-by: Rex Fu <[email protected]>
> ---
>  arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 10
> +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> index 2cb7bd128d24..fe960bb7bc27 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> @@ -912,7 +912,7 @@ &sgpiom0 {
>       "PWRGD_PVDDIO_P0", "",
>       "PWRGD_PVDDIO_MEM_S3_P0", "",
>       "PWRGD_CHMP_CPU0_FPGA", "",
> -     "PWRGD_CHIL_CPU0_FPGA", "",
> +     "HPM_EDSFF_PG", "",
>       "PWRGD_CHEH_CPU0_FPGA", "",
>       "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
>       "", "",
> @@ -957,8 +957,8 @@ &sgpiom0 {
>       "PDB_ALERT_R_N", "",
>
>       /* L0-L7 line 176-191 */
> -     "CPU0_SP7R1", "", "CPU0_SP7R2", "",
> -     "CPU0_SP7R3", "", "CPU0_SP7R4", "",
> +     "L_EDSFF2_PG", "", "L_EDSFF3_PG", "",
> +     "R_EDSFF2_PG", "", "R_EDSFF3_PG", "",
>       "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
>       "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
>
> @@ -984,8 +984,8 @@ &sgpiom0 {
>       "HPM_PWR_FAIL", "Port80_b0",
>       "FM_DIMM_IP_FAIL", "Port80_b1",
>       "FM_DIMM_AH_FAIL", "Port80_b2",
> -     "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
> -     "FM_CPU0_THERMTRIP_N", "Port80_b4",
> +     "AMC_THERMTRIP_ASSERT", "Port80_b3",
> +     "CPU_THERMTRIP_ASSERT", "Port80_b4",
>       "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
>       "CPLD_SGPIO_RDY", "Port80_b6",
>       "", "Port80_b7",
>
> ---
> base-commit: 9974969c14031a097d6b45bcb7a06bb4aa525c40
> change-id: 20260430-anacapa-sgpio-edsff-thermtrip-acb228bf61be
>
> Best regards,
> --
> Rex Fu <[email protected]>
>