RE: [PATCH] dt-bindings: usb: Add Aspeed AST2700 DWC3 controller

> Subject: Re: [PATCH] dt-bindings: usb: Add Aspeed AST2700 DWC3 controller
> 
> On Tue, Jul 07, 2026 at 02:12:04PM +0800, Ryan Chen wrote:
> > The Aspeed AST2700 SoC integrates the Synopsys DesignWare USB3 core
> > with no vendor glue logic: it is functionally compatible with
> > snps,dwc3, uses the standard DWC3 clocks, and the only SoC-specific
> > part is a USB3 PHY that is handled by a separate driver.
> >
> > Add a dedicated binding document rather than adding the compatible and
> > a conditional to snps,dwc3.yaml. This follows the established
> > per-vendor DWC3 convention (apple,dwc3.yaml,
> > socionext,uniphier-dwc3.yaml, ...) and keeps the AST2700-specific
> > constraints - notably the mandatory USB3 PHY - out of the generic schema.
> >
> > Signed-off-by: Ryan Chen <[email protected]>
> > ---
> 
> Why are clocks unconstrained?
> 
They shouldn't be - I'll add the constraints in this schema:

  clocks:
    items:
      - description: Controller bus early clock
      - description: PHY reference clock
      - description: Controller suspend clock

  clock-names:
    items:
      - const: bus_early
      - const: ref
      - const: suspend