[RFC 1/3] Floating Point changes

From: Dave Patel <[email protected]>

Signed-off-by: Dave Patel <[email protected]>
---
 core/arch/riscv/include/riscv_fp.h |  30 ++++++
 core/arch/riscv/kernel/riscv_fp.S  | 159 +++++++++++++++++++++++++++++
 2 files changed, 189 insertions(+)
 create mode 100644 core/arch/riscv/include/riscv_fp.h
 create mode 100644 core/arch/riscv/kernel/riscv_fp.S

diff --git a/core/arch/riscv/include/riscv_fp.h b/core/arch/riscv/include/riscv_fp.h
new file mode 100644
index 000000000..19faf925f
--- /dev/null
+++ b/core/arch/riscv/include/riscv_fp.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2026, RISCStar Limited
+ */
+
+#ifndef __KERNEL_RISCV_FP_H
+#define __KERNEL_RISCV_FP_H
+
+#include <types_ext.h>
+#include <compiler.h>
+
+/* CSR Status Bit Masks for Floating-Point Extensions */
+#define SSTATUS_FS_MASK       SHIFT_U32(3, 13)  /* bits [14:13] */
+#define SSTATUS_FS_OFF        SHIFT_U32(0, 13)
+#define SSTATUS_FS_INITIAL    SHIFT_U32(1, 13)
+#define SSTATUS_FS_CLEAN      SHIFT_U32(2, 13)
+#define SSTATUS_FS_DIRTY      SHIFT_U32(3, 13)
+
+/* Floating-Point Context Struct */
+struct riscv_fp_state {
+#if __riscv_xlen == 64
+	uint64_t fpregs[32];
+#elif __riscv_xlen == 32
+	uint32_t fpregs[32];
+#endif
+	unsigned long fcsr;
+};
+
+#endif /* __KERNEL_RISCV_FP_H */
+
diff --git a/core/arch/riscv/kernel/riscv_fp.S b/core/arch/riscv/kernel/riscv_fp.S
new file mode 100644
index 000000000..4fa53649e
--- /dev/null
+++ b/core/arch/riscv/kernel/riscv_fp.S
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2026, RISCStar Limited
+ */
+
+#include <asm.h>
+
+/* void __asm_save_fp_state */
+FUNC __asm_save_fp_state , :
+#if __riscv_xlen == 64
+	fsd f0,   0(a0)
+	fsd f1,   8(a0)
+	fsd f2,   16(a0)
+	fsd f3,   24(a0)
+	fsd f4,   32(a0)
+	fsd f5,   40(a0)
+	fsd f6,   48(a0)
+	fsd f7,   56(a0)
+	fsd f8,   64(a0)
+	fsd f9,   72(a0)
+	fsd f10,  80(a0)
+	fsd f11,  88(a0)
+	fsd f12,  96(a0)
+	fsd f13,  104(a0)
+	fsd f14,  112(a0)
+	fsd f15,  120(a0)
+	fsd f16,  128(a0)
+	fsd f17,  136(a0)
+	fsd f18,  144(a0)
+	fsd f19,  152(a0)
+	fsd f20,  160(a0)
+	fsd f21,  168(a0)
+	fsd f22,  176(a0)
+	fsd f23,  184(a0)
+	fsd f24,  192(a0)
+	fsd f25,  200(a0)
+	fsd f26,  208(a0)
+	fsd f27,  216(a0)
+	fsd f28,  224(a0)
+	fsd f29,  232(a0)
+	fsd f30,  240(a0)
+	fsd f31,  248(a0)
+	csrr t0, fcsr
+	sd t0, 256(a0)
+#elif __riscv_xlen == 32
+	fsw f0,   0(a0)
+	fsw f1,   4(a0)
+	fsw f2,   8(a0)
+	fsw f3,   12(a0)
+	fsw f4,   16(a0)
+	fsw f5,   20(a0)
+	fsw f6,   24(a0)
+	fsw f7,   28(a0)
+	fsw f8,   32(a0)
+	fsw f9,   36(a0)
+	fsw f10,  40(a0)
+	fsw f11,  44(a0)
+	fsw f12,  48(a0)
+	fsw f13,  52(a0)
+	fsw f14,  56(a0)
+	fsw f15,  60(a0)
+	fsw f16,  64(a0)
+	fsw f17,  68(a0)
+	fsw f18,  72(a0)
+	fsw f19,  76(a0)
+	fsw f20,  80(a0)
+	fsw f21,  84(a0)
+	fsw f22,  88(a0)
+	fsw f23,  92(a0)
+	fsw f24,  96(a0)
+	fsw f25,  100(a0)
+	fsw f26,  104(a0)
+	fsw f27,  108(a0)
+	fsw f28,  112(a0)
+	fsw f29,  116(a0)
+	fsw f30,  120(a0)
+	fsw f31,  124(a0)
+	csrr t0, fcsr
+	sw t0, 128(a0)
+#endif
+	ret
+END_FUNC __asm_save_fp_state
+
+/* void __asm_restore_fp_state */
+FUNC __asm_restore_fp_state , :
+#if __riscv_xlen == 64
+	ld t0, 256(a0)
+	csrw fcsr, t0
+	fld f0,   0(a0)
+	fld f1,   8(a0)
+	fld f2,   16(a0)
+	fld f3,   24(a0)
+	fld f4,   32(a0)
+	fld f5,   40(a0)
+	fld f6,   48(a0)
+	fld f7,   56(a0)
+	fld f8,   64(a0)
+	fld f9,   72(a0)
+	fld f10,  80(a0)
+	fld f11,  88(a0)
+	fld f12,  96(a0)
+	fld f13,  104(a0)
+	fld f14,  112(a0)
+	fld f15,  120(a0)
+	fld f16,  128(a0)
+	fld f17,  136(a0)
+	fld f18,  144(a0)
+	fld f19,  152(a0)
+	fld f20,  160(a0)
+	fld f21,  168(a0)
+	fld f22,  176(a0)
+	fld f23,  184(a0)
+	fld f24,  192(a0)
+	fld f25,  200(a0)
+	fld f26,  208(a0)
+	fld f27,  216(a0)
+	fld f28,  224(a0)
+	fld f29,  232(a0)
+	fld f30,  240(a0)
+	fld f31,  248(a0)
+#elif __riscv_xlen == 32
+	lw t0, 128(a0)
+	csrw fcsr, t0
+	flw f0,   0(a0)
+	flw f1,   4(a0)
+	flw f2,   8(a0)
+	flw f3,   12(a0)
+	flw f4,   16(a0)
+	flw f5,   20(a0)
+	flw f6,   24(a0)
+	flw f7,   28(a0)
+	flw f8,   32(a0)
+	flw f9,   36(a0)
+	flw f10,  40(a0)
+	flw f11,  44(a0)
+	flw f12,  48(a0)
+	flw f13,  52(a0)
+	flw f14,  56(a0)
+	flw f15,  60(a0)
+	flw f16,  64(a0)
+	flw f17,  68(a0)
+	flw f18,  72(a0)
+	flw f19,  76(a0)
+	flw f20,  80(a0)
+	flw f21,  84(a0)
+	flw f22,  88(a0)
+	flw f23,  92(a0)
+	flw f24,  96(a0)
+	flw f25,  100(a0)
+	f_lw f26,  104(a0)
+	flw f27,  108(a0)
+	flw f28,  112(a0)
+	flw f29,  116(a0)
+	flw f30,  120(a0)
+	flw f31,  124(a0)
+#endif
+	ret
+END_FUNC __asm_restore_fp_state
+
-- 
2.43.0