[PATCH 15/17] ARM: dts: r9a06g032: add QSPI controller
Ralph Siemsen <[email protected]>
| Newsgroups | org.u-boot-project.lists.u-boot |
|---|---|
| Message-ID | <[email protected]> |
The RZ/N1 has a Quad-SPI controller based on Cadence IP core. Signed-off-by: Ralph Siemsen <[email protected]> --- This change needs to go to upstream DTS. --- arch/arm/dts/r9a06g032.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi index f4f760aff28..b9073abc7f7 100644 --- a/arch/arm/dts/r9a06g032.dtsi +++ b/arch/arm/dts/r9a06g032.dtsi @@ -66,6 +66,19 @@ #size-cells = <1>; ranges; + qspi0: spi@40005000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005000 0x1000>, + <0x10000000 0x10000000>; + reg-names = "qspi", "qspi-mapping"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_QSPI0>, <&sysctrl R9A06G032_CLK_QSPI0>; + clock-names = "flexway", "pclk"; + status = "disabled"; + }; + rtc0: rtc@40006000 { compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg = <0x40006000 0x1000>; -- 2.55.0