[PATCH v3 6/7] riscv: dts: sophgo: Drop local CV18xx devicetrees
Zhuxu Ran via U-Boot <[email protected]>
| Newsgroups | org.u-boot-project.lists.u-boot |
|---|---|
| Message-ID | <[email protected]> |
Milk-V Duo and LicheeRV Nano now use the upstream CV1800B and SG2002 devicetrees. Remove the unused local devicetree files and their Makefile entries. Signed-off-by: Zhuxu Ran <[email protected]> --- arch/riscv/dts/Makefile | 2 - arch/riscv/dts/cv1800b-milkv-duo.dts | 64 --------- arch/riscv/dts/cv1800b.dtsi | 22 --- arch/riscv/dts/cv18xx.dtsi | 232 ------------------------------ arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 ------ arch/riscv/dts/sg2002.dtsi | 34 ----- 6 files changed, 399 deletions(-) diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 71c5c13d221..c588ce546bf 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -4,8 +4,6 @@ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb -dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb -dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts deleted file mode 100644 index e7cc0e8bd14..00000000000 --- a/arch/riscv/dts/cv1800b-milkv-duo.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 Jisheng Zhang <[email protected]> - */ - -/dts-v1/; - -#include "cv1800b.dtsi" - -/ { - model = "Milk-V Duo"; - compatible = "milkv,duo", "sophgo,cv1800b"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x3f40000>; - }; -}; - -ðernet0 { - status = "okay"; - phy-mode = "rmii"; -}; - -&osc { - clock-frequency = <25000000>; -}; - -&sdhci0 { - status = "okay"; - bus-width = <4>; - no-1-8-v; - no-mmc; - no-sdio; -}; - -&spif { - status = "okay"; - - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <75000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi deleted file mode 100644 index baf641829e7..00000000000 --- a/arch/riscv/dts/cv1800b.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 Jisheng Zhang <[email protected]> - */ - -#include "cv18xx.dtsi" - -/ { - compatible = "sophgo,cv1800b"; -}; - -&plic { - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; -}; - -&clint { - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; -}; - -&clk { - compatible = "sophgo,cv1800-clk"; -}; diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi deleted file mode 100644 index 8530527aa39..00000000000 --- a/arch/riscv/dts/cv18xx.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 Jisheng Zhang <[email protected]> - * Copyright (C) 2023 Inochi Amaoto <[email protected]> - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/clock/sophgo,cv1800.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <25000000>; - - cpu0: cpu@0 { - compatible = "thead,c906", "riscv"; - device_type = "cpu"; - reg = <0>; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <65536>; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - mmu-type = "riscv,sv39"; - riscv,isa = "rv64imafdc"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_25m"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <1>; - #size-cells = <1>; - dma-noncoherent; - ranges; - - clk: clock-controller@3002000 { - reg = <0x03002000 0x1000>; - clocks = <&osc>; - #clock-cells = <1>; - }; - - gpio0: gpio@3020000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3020000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@3021000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3021000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio2: gpio@3022000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3022000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio3: gpio@3023000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3023000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - ethernet0: ethernet@4070000 { - compatible = "sophgo,cv1800b-dwmac"; - reg = <0x04070000 0x10000>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_ETH0_500M>, <&clk CLK_AXI4_ETH0>; - clock-names = "stmmaceth", "pclk"; - status = "disabled"; - }; - - uart0: serial@4140000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04140000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@4150000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04150000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@4160000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04160000 0x100>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@4170000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04170000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@41c0000 { - compatible = "snps,dw-apb-uart"; - reg = <0x041c0000 0x100>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - sdhci0: mmc@4310000 { - compatible = "sophgo,cv1800b-dwcmshc"; - reg = <0x4310000 0x1000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>; - clock-names = "core", "bus"; - status = "disabled"; - }; - - spif: spi@10000000 { - compatible = "sophgo,cv1800b-spif"; - reg = <0x10000000 0x10000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLK_AHB_SF>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - plic: interrupt-controller@70000000 { - reg = <0x70000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <101>; - }; - - clint: timer@74000000 { - reg = <0x74000000 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; - }; - }; -}; diff --git a/arch/riscv/dts/sg2002-licheerv-nano-b.dts b/arch/riscv/dts/sg2002-licheerv-nano-b.dts deleted file mode 100644 index 9871a75836c..00000000000 --- a/arch/riscv/dts/sg2002-licheerv-nano-b.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2024 Thomas Bonnefille <[email protected]> - */ - -/dts-v1/; - -#include "sg2002.dtsi" - -/ { - model = "LicheeRV Nano B"; - compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&osc { - clock-frequency = <25000000>; -}; - -&sdhci0 { - status = "okay"; - bus-width = <4>; - no-1-8-v; - no-mmc; - no-sdio; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/riscv/dts/sg2002.dtsi b/arch/riscv/dts/sg2002.dtsi deleted file mode 100644 index 0f97000fa8b..00000000000 --- a/arch/riscv/dts/sg2002.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2024 Thomas Bonnefille <[email protected]> - */ - -/dts-v1/; - -#include <dt-bindings/interrupt-controller/irq.h> -#include "cv18xx.dtsi" - -/ { - compatible = "sophgo,sg2002"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&plic { - compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-plic", "thead,c900-plic"; -}; - -&clint { - compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-clint", "thead,c900-clint"; -}; - -&clk { - compatible = "sophgo,sg2002-clk", "sophgo,cv1800-clk"; -}; - -&sdhci0 { - compatible = "sophgo,sg2002-dwcmshc", "sophgo,cv1800b-dwcmshc"; -}; -- 2.55.0