Re: [PATCH 08/15] clk: rockchip: rk3588: Fix possible divide by zero

Hi Jonas,

On 7/30/26 4:12 PM, Jonas Karlman wrote:
> The best rate handling of rk3588_dclk_vop_set_clk() may unintentionally
> trigger a divide by zero when V0PLL is tested as parent. Instead, fully
> skip rate calculation when testing using V0PLL as parent to avoid a
> divide by zero error.
> 

Reviewed-by: Quentin Schulz <[email protected]>

Thanks!
Quentin