[PATCH v2 1/2] dt-bindings: clock: add MT8366 clock header
David Lechner <[email protected]>
| Newsgroups | org.u-boot-project.lists.u-boot |
|---|---|
| Message-ID | <[email protected]> |
From: Irving-CH Lin <[email protected]> Add a header with MT8366 clock definitions for use in devicetrees. Upstreaming of MT8366 has not even started yet, so we will have to carry a downstream version of this for some time. Signed-off-by: Irving-CH Lin <[email protected]> Signed-off-by: David Lechner <[email protected]> --- MAINTAINERS | 1 + include/dt-bindings/clock/mt8366-clk.h | 473 +++++++++++++++++++++++++++++++++ 2 files changed, 474 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d0924f72af4..4505299f89a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1332,6 +1332,7 @@ F: include/configs/mt7621.h F: include/dt-bindings/clock/mt7620-clk.h F: include/dt-bindings/clock/mt7621-clk.h F: include/dt-bindings/clock/mt7628-clk.h +F: include/dt-bindings/clock/mt8366-clk.h F: include/dt-bindings/reset/mt7620-reset.h F: include/dt-bindings/reset/mt7621-reset.h F: include/dt-bindings/reset/mt7628-reset.h diff --git a/include/dt-bindings/clock/mt8366-clk.h b/include/dt-bindings/clock/mt8366-clk.h new file mode 100644 index 00000000000..9bf37db5cff --- /dev/null +++ b/include/dt-bindings/clock/mt8366-clk.h @@ -0,0 +1,473 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2026 MediaTek Inc. + * Author: Irving-CH Lin <[email protected]> + */ + +#ifndef _DT_BINDINGS_CLK_MT8366_H +#define _DT_BINDINGS_CLK_MT8366_H + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_BL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_APLL1 3 +#define CLK_APMIXED_APLL2 4 +#define CLK_APMIXED_APLL3 5 +#define CLK_APMIXED_APLL4 6 +#define CLK_APMIXED_APLL5 7 +#define CLK_APMIXED_MAINPLL 8 +#define CLK_APMIXED_UNIVPLL 9 +#define CLK_APMIXED_MMPLL 10 +#define CLK_APMIXED_TVDPLL1 11 +#define CLK_APMIXED_TVDPLL2 12 +#define CLK_APMIXED_MSDCPLL 13 +#define CLK_APMIXED_MFGPLL 14 +#define CLK_APMIXED_APUPLL2 15 +#define CLK_APMIXED_APUPLL 16 +#define CLK_APMIXED_ETHPLL 17 +#define CLK_APMIXED_CANPLL 18 +#define CLK_APMIXED_EMIPLL 19 + +/* TOPCKGEN */ +#define CLK_TOP_AXI_SEL 0 +#define CLK_TOP_SPM_SEL 1 +#define CLK_TOP_BUS_AXIMEM_SEL 2 +#define CLK_TOP_DISP_SEL 3 +#define CLK_TOP_EPD_SEL 4 +#define CLK_TOP_MDP_SEL 5 +#define CLK_TOP_DP_SEL 6 +#define CLK_TOP_IMG1_SEL 7 +#define CLK_TOP_IPE_SEL 8 +#define CLK_TOP_CAM_SEL 9 +#define CLK_TOP_CAMTM_SEL 10 +#define CLK_TOP_CAMTG_SEL 11 +#define CLK_TOP_CAMTG2_SEL 12 +#define CLK_TOP_MFG_REF_SEL 13 +#define CLK_TOP_UART_SEL 14 +#define CLK_TOP_SPI0_SEL 15 +#define CLK_TOP_SPI1_SEL 16 +#define CLK_TOP_SPI2_SEL 17 +#define CLK_TOP_SPI3_SEL 18 +#define CLK_TOP_SPI4_SEL 19 +#define CLK_TOP_SPI5_SEL 20 +#define CLK_TOP_I2CP_SEL 21 +#define CLK_TOP_I2C_SEL 22 +#define CLK_TOP_SENINF_SEL 23 +#define CLK_TOP_SENINF1_SEL 24 +#define CLK_TOP_VENC_SEL 25 +#define CLK_TOP_VDEC_SEL 26 +#define CLK_TOP_PWM_SEL 27 +#define CLK_TOP_DVFSRC_SEL 28 +#define CLK_TOP_AES_MSDCFBE_SEL 29 +#define CLK_TOP_MSDC_MACRO_0P_SEL 30 +#define CLK_TOP_MSDC_MACRO_1P_SEL 31 +#define CLK_TOP_MSDC_MACRO_2P_SEL 32 +#define CLK_TOP_MSDC50_0_SEL 33 +#define CLK_TOP_MSDC30_1_SEL 34 +#define CLK_TOP_MSDC30_2_SEL 35 +#define CLK_TOP_MSDC50_0_HCLK_SEL 36 +#define CLK_TOP_MSDC30_1_HCLK_SEL 37 +#define CLK_TOP_MSDC30_2_HCLK_SEL 38 +#define CLK_TOP_MCUPM_SEL 39 +#define CLK_TOP_DSI_OCC_SEL 40 +#define CLK_TOP_KP_IRQ_GEN_SEL 41 +#define CLK_TOP_NFI_BCLK_SEL 42 +#define CLK_TOP_SFLASH_SEL 43 +#define CLK_TOP_EMI_SEL 44 +#define CLK_TOP_MAC_TL_SEL 45 +#define CLK_TOP_SNPS_ETH_250M_SEL 46 +#define CLK_TOP_SNPS_ETH_62P4M_PTP_SEL 47 +#define CLK_TOP_SNPS_ETH_50M_RMII_SEL 48 +#define CLK_TOP_LVDSTX_CLKDIG_CTS_SEL 49 +#define CLK_TOP_VPLL_DPIX_SEL 50 +#define CLK_TOP_EPD_DPI_SEL 51 +#define CLK_TOP_DSP_SEL 52 +#define CLK_TOP_ECC_SEL 53 +#define CLK_TOP_GCPU_SEL 54 +#define CLK_TOP_USB_TOP_P0_SEL 55 +#define CLK_TOP_USB_XHCI_P0_SEL 56 +#define CLK_TOP_USB_TOP_P1_SEL 57 +#define CLK_TOP_USB_XHCI_P1_SEL 58 +#define CLK_TOP_USB_TOP_P2_SEL 59 +#define CLK_TOP_USB_XHCI_P2_SEL 60 +#define CLK_TOP_AUD_INTBUS_SEL 61 +#define CLK_TOP_AUD_ENGEN1_SEL 62 +#define CLK_TOP_AUD_ENGEN2_SEL 63 +#define CLK_TOP_EARC_ENGEN_SEL 64 +#define CLK_TOP_SPDIFIN_ENGEN_SEL 65 +#define CLK_TOP_LINEIN_ENGEN_SEL 66 +#define CLK_TOP_AUDIO_H_SEL 67 +#define CLK_TOP_VADSP_VOWPLL_SEL 68 +#define CLK_TOP_PWRAP_ULPOSC_SEL 69 +#define CLK_TOP_AUD_1_SEL 70 +#define CLK_TOP_AUD_2_SEL 71 +#define CLK_TOP_VADSP_26M_SEL 72 +#define CLK_TOP_ATB_SEL 73 +#define CLK_TOP_ASM_H_SEL 74 +#define CLK_TOP_I2SI4_M_SEL 75 +#define CLK_TOP_I2SI6_M_SEL 76 +#define CLK_TOP_I2SO4_M_SEL 77 +#define CLK_TOP_I2SO5_M_SEL 78 +#define CLK_TOP_I2SO6_M_SEL 79 +#define CLK_TOP_AUD_IEC_SEL 80 +#define CLK_TOP_SPDIFIN_SEL 81 +#define CLK_TOP_CAN0_SEL 82 +#define CLK_TOP_DISP_PWM_SEL 83 +#define CLK_TOP_SSPM_SEL 84 +#define CLK_TOP_VADSP_SEL 85 +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 86 +#define CLK_TOP_MFG_SEL_MFGPLL 87 +#define CLK_TOP_APLL12_CK_DIV_I2SIN5 88 +#define CLK_TOP_APLL12_CK_DIV_I2SIN6 89 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT4 90 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT5 91 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT6 92 +#define CLK_TOP_APLL12_CK_DIV_SPDIFOUT 93 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 94 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 95 +#define CLK_TOP_MAINPLL_D4 96 +#define CLK_TOP_MAINPLL_D4_D2 97 +#define CLK_TOP_MAINPLL_D4_D4 98 +#define CLK_TOP_MAINPLL_D4_D8 99 +#define CLK_TOP_MAINPLL_D5 100 +#define CLK_TOP_MAINPLL_D5_D2 101 +#define CLK_TOP_MAINPLL_D6 102 +#define CLK_TOP_MAINPLL_D6_D2 103 +#define CLK_TOP_MAINPLL_D6_D4 104 +#define CLK_TOP_MAINPLL_D7_D2 105 +#define CLK_TOP_MAINPLL_D7_D4 106 +#define CLK_TOP_MAINPLL_D7_D8 107 +#define CLK_TOP_MAINPLL_D9 108 +#define CLK_TOP_UNIVPLL_D4 109 +#define CLK_TOP_UNIVPLL_D4_D2 110 +#define CLK_TOP_UNIVPLL_D4_D4 111 +#define CLK_TOP_UNIVPLL_D4_D8 112 +#define CLK_TOP_UNIVPLL_D5 113 +#define CLK_TOP_UNIVPLL_D5_D2 114 +#define CLK_TOP_UNIVPLL_D5_D4 115 +#define CLK_TOP_UNIVPLL_D5_D8 116 +#define CLK_TOP_UNIVPLL_D6 117 +#define CLK_TOP_UNIVPLL_D6_D2 118 +#define CLK_TOP_UNIVPLL_D6_D4 119 +#define CLK_TOP_UNIVPLL_D6_D8 120 +#define CLK_TOP_UNIVPLL_D6_D16 121 +#define CLK_TOP_UNIVPLL_D7 122 +#define CLK_TOP_UNIVPLL_D7_D2 123 +#define CLK_TOP_UNIVPLL_D7_D3 124 +#define CLK_TOP_UNIVPLL_192M_D2 125 +#define CLK_TOP_UNIVPLL_192M_D4 126 +#define CLK_TOP_UNIVPLL_192M_D8 127 +#define CLK_TOP_UNIVPLL_192M_D16 128 +#define CLK_TOP_UNIVPLL_192M_D32 129 +#define CLK_TOP_UNIVPLL_192M_D10 130 +#define CLK_TOP_APLL1_D4 131 +#define CLK_TOP_APLL1_D3 132 +#define CLK_TOP_APLL2_D4 133 +#define CLK_TOP_APLL2_D3 134 +#define CLK_TOP_APLL3_D4 135 +#define CLK_TOP_APLL4_D4 136 +#define CLK_TOP_APLL5_D4 137 +#define CLK_TOP_MMPLL_D4 138 +#define CLK_TOP_MMPLL_D4_D2 139 +#define CLK_TOP_MMPLL_D4_D4 140 +#define CLK_TOP_MMPLL_D5 141 +#define CLK_TOP_MMPLL_D5_D2 142 +#define CLK_TOP_MMPLL_D6 143 +#define CLK_TOP_MMPLL_D6_D2 144 +#define CLK_TOP_MMPLL_D7 145 +#define CLK_TOP_TVDPLL1_D2 146 +#define CLK_TOP_TVDPLL1_D4 147 +#define CLK_TOP_TVDPLL1_D8 148 +#define CLK_TOP_TVDPLL1_D16 149 +#define CLK_TOP_TVDPLL2_D4 150 +#define CLK_TOP_TVDPLL2_D8 151 +#define CLK_TOP_MSDCPLL_D2 152 +#define CLK_TOP_ETHPLL_D2 153 +#define CLK_TOP_ETHPLL_D8 154 +#define CLK_TOP_ETHPLL_D10 155 +#define CLK_TOP_CANPLL_D5 156 +#define CLK_TOP_CANPLL_D10 157 +#define CLK_TOP_CANPLL_D20 158 +#define CLK_TOP_CANPLL_D25 159 +#define CLK_TOP_OSC_D2 160 +#define CLK_TOP_OSC_D4 161 +#define CLK_TOP_OSC_D8 162 +#define CLK_TOP_OSC_D16 163 +#define CLK_TOP_OSC_D10 164 +#define CLK_TOP_OSC_D20 165 +#define CLK_TOP_APLL12_DIV_I2SIN0_PDN 166 +#define CLK_TOP_APLL12_DIV_I2SIN1_PDN 167 +#define CLK_TOP_APLL12_DIV_I2SIN2_PDN 168 +#define CLK_TOP_APLL12_DIV_I2SIN3_PDN 169 +#define CLK_TOP_APLL12_DIV_I2SIN4_PDN 170 +#define CLK_TOP_APLL12_DIV_I2SIN6_PDN 171 +#define CLK_TOP_APLL12_DIV_I2SOUT0_PDN 172 +#define CLK_TOP_APLL12_DIV_I2SOUT1_PDN 173 +#define CLK_TOP_APLL12_DIV_I2SOUT2_PDN 174 +#define CLK_TOP_APLL12_DIV_I2SOUT3_PDN 175 +#define CLK_TOP_APLL12_DIV_I2SOUT4_PDN 176 +#define CLK_TOP_APLL12_DIV_I2SOUT5_PDN 177 +#define CLK_TOP_APLL12_DIV_I2SOUT6_PDN 178 +#define CLK_TOP_APLL12_DIV_SPDIFOUT_PDN 179 +#define CLK_TOP_APLL12_DIV_TDMOUT_M_PDN 180 +#define CLK_TOP_APLL12_DIV_TDMOUT_B_PDN 181 +#define CLK_TOP_F26M_CK_EN 182 +#define CLK_TOP_USB_F26M_CK_EN 183 +#define CLK_TOP_USB2_PHY_REFCK_P0_EN 184 +#define CLK_TOP_USB2_PHY_REFCK_P1_EN 185 +#define CLK_TOP_USB2_PHY_REFCK_P2_EN 186 +#define CLK_TOP_USB2_26M_CK_P0_EN 187 +#define CLK_TOP_USB2_26M_CK_P1_EN 188 +#define CLK_TOP_USB2_26M_CK_P2_EN 189 +#define CLK_TOP_FMCNT_P0_EN 190 +#define CLK_TOP_FMCNT_P1_EN 191 +#define CLK_TOP_FMCNT_P2_EN 192 + +/* INFRACFG_AO_REG */ +#define CLK_INFRACFG_AO_REGP_UART0 0 +#define CLK_INFRACFG_AO_REGP_UART1 1 +#define CLK_INFRACFG_AO_REGP_UART2 2 +#define CLK_INFRACFG_AO_REGP_UART3 3 +#define CLK_INFRACFG_AO_REGP_DISP_PWM0 4 +#define CLK_INFRACFG_AO_REGP_DISP_PWM1 5 +#define CLK_INFRACFG_AO_REGP_SPI0_B 6 +#define CLK_INFRACFG_AO_REGP_SPI1_B 7 +#define CLK_INFRACFG_AO_REGP_SPI2_B 8 +#define CLK_INFRACFG_AO_REGP_SPI3_B 9 +#define CLK_INFRACFG_AO_REGP_SPI4_B 10 +#define CLK_INFRACFG_AO_REGP_SPI5_B 11 +#define CLK_INFRACFG_AO_REGP_SPI0_H 12 +#define CLK_INFRACFG_AO_REGP_SPI1_H 13 +#define CLK_INFRACFG_AO_REGP_SPI2_H 14 +#define CLK_INFRACFG_AO_REGP_SPI3_H 15 +#define CLK_INFRACFG_AO_REGP_SPI4_H 16 +#define CLK_INFRACFG_AO_REGP_SPI5_H 17 +#define CLK_INFRACFG_AO_REGP_AXI 18 +#define CLK_INFRACFG_AO_REGP_AHB 19 +#define CLK_INFRACFG_AO_REGP_TL 20 +#define CLK_INFRACFG_AO_REGP_REF 21 +#define CLK_INFRACFG_AO_REGP_DMA_B 22 +#define CLK_INFRACFG_AO_REGP_SSUSB0_PIPE 23 +#define CLK_INFRACFG_AO_REGP_SSUSB0_REF 24 +#define CLK_INFRACFG_AO_REGP_SSUSB0_FRMCNT 25 +#define CLK_INFRACFG_AO_REGP_SSUSB0_UTMI 26 +#define CLK_INFRACFG_AO_REGP_SSUSB0_SYS 27 +#define CLK_INFRACFG_AO_REGP_SSUSB0_XCHI 28 +#define CLK_INFRACFG_AO_REGP_SSUSB0_F 29 +#define CLK_INFRACFG_AO_REGP_SSUSB0_H 30 +#define CLK_INFRACFG_AO_REGP_SSUSB1_REF 31 +#define CLK_INFRACFG_AO_REGP_SSUSB1_FRMCNT 32 +#define CLK_INFRACFG_AO_REGP_SSUSB1_UTMI 33 +#define CLK_INFRACFG_AO_REGP_SSUSB1_SYS 34 +#define CLK_INFRACFG_AO_REGP_SSUSB1_XCHI 35 +#define CLK_INFRACFG_AO_REGP_SSUSB1_F 36 +#define CLK_INFRACFG_AO_REGP_SSUSB1_H 37 +#define CLK_INFRACFG_AO_REGP_SSUSB2_REF 38 +#define CLK_INFRACFG_AO_REGP_SSUSB2_FRMCNT 39 +#define CLK_INFRACFG_AO_REGP_SSUSB2_UTMI 40 +#define CLK_INFRACFG_AO_REGP_SSUSB2_SYS 41 +#define CLK_INFRACFG_AO_REGP_SSUSB2_XCHI 42 +#define CLK_INFRACFG_AO_REGP_SSUSB2_F 43 +#define CLK_INFRACFG_AO_REGP_SSUSB2_H 44 +#define CLK_INFRACFG_AO_REG_PMIC_TMR 45 +#define CLK_INFRACFG_AO_REG_PMIC_AP 46 +#define CLK_INFRACFG_AO_REG_SEJ 47 +#define CLK_INFRACFG_AO_REG_MCUPM 48 +#define CLK_INFRACFG_AO_REG_GCE 49 +#define CLK_INFRACFG_AO_REG_GCE2 50 +#define CLK_INFRACFG_AO_REG_PWM_H 51 +#define CLK_INFRACFG_AO_REG_PWM1 52 +#define CLK_INFRACFG_AO_REG_PWM2 53 +#define CLK_INFRACFG_AO_REG_PWM3 54 +#define CLK_INFRACFG_AO_REG_PWM4 55 +#define CLK_INFRACFG_AO_REG_PWM 56 +#define CLK_INFRACFG_AO_REG_GCE_26M 57 +#define CLK_INFRACFG_AO_REG_CQ_DMA_FPC 58 +#define CLK_INFRACFG_AO_REG_BTIF 59 +#define CLK_INFRACFG_AO_REG_SPI0 60 +#define CLK_INFRACFG_AO_REG_AUXADC 61 +#define CLK_INFRACFG_AO_REG_CPUM 62 +#define CLK_INFRACFG_AO_REG_CCIF1_AP 63 +#define CLK_INFRACFG_AO_REG_CCIF1_MD 64 +#define CLK_INFRACFG_AO_REG_AUXADC_MD 65 +#define CLK_INFRACFG_AO_REG_TL_26M 66 +#define CLK_INFRACFG_AO_REG_TL_96M 67 +#define CLK_INFRACFG_AO_REG_PL_P_250M 68 +#define CLK_INFRACFG_AO_REG_CCIF_AP 69 +#define CLK_INFRACFG_AO_REG_DEBUGSYS 70 +#define CLK_INFRACFG_AO_REG_AUDIO 71 +#define CLK_INFRACFG_AO_REG_CCIF_MD 72 +#define CLK_INFRACFG_AO_REG_DBG_TRACE 73 +#define CLK_INFRACFG_AO_REG_CLDMA_BCLK 74 +#define CLK_INFRACFG_AO_REG_AUDIO_26M_BCLK 75 +#define CLK_INFRACFG_AO_REG_MODEM_TEMP_SHARE 76 +#define CLK_INFRACFG_AO_REG_SPI1 77 +#define CLK_INFRACFG_AO_REG_SPI2 78 +#define CLK_INFRACFG_AO_REG_SPI3 79 +#define CLK_INFRACFG_AO_REG_U_SAP_B 80 +#define CLK_INFRACFG_AO_REG_UNIPRO_MBIST 81 +#define CLK_INFRACFG_AO_REG_SPI4 82 +#define CLK_INFRACFG_AO_REG_SPI5 83 +#define CLK_INFRACFG_AO_REG_CQ_DMA 84 +#define CLK_INFRACFG_AO_REG_KP_IRQ_GEN 85 +#define CLK_INFRACFG_AO_REG_KP_32K 86 +#define CLK_INFRACFG_AO_REG_U_AXI 87 +#define CLK_INFRACFG_AO_REG_CCIF5_AP 88 +#define CLK_INFRACFG_AO_REG_CCIF5_MD 89 +#define CLK_INFRACFG_AO_REG_CCIF2_AP 90 +#define CLK_INFRACFG_AO_REG_CCIF2_MD 91 +#define CLK_INFRACFG_AO_REG_CCIF3_AP 92 +#define CLK_INFRACFG_AO_REG_CCIF3_MD 93 +#define CLK_INFRACFG_AO_REG_SEJ_F13M 94 +#define CLK_INFRACFG_AO_REG_AES 95 +#define CLK_INFRACFG_AO_REG_GCPU 96 +#define CLK_INFRACFG_AO_REG_ECC 97 +#define CLK_INFRACFG_AO_REG_CCIF4_AP 98 +#define CLK_INFRACFG_AO_REG_CCIF4_MD 99 +#define CLK_INFRACFG_AO_REGP_AUXADC_26M 100 +#define CLK_INFRACFG_AO_REGP_MSDC0 101 +#define CLK_INFRACFG_AO_REGP_MSDC0_H 102 +#define CLK_INFRACFG_AO_REGP_MSDC0_FAES 103 +#define CLK_INFRACFG_AO_REGP_MSDC0_MST_F 104 +#define CLK_INFRACFG_AO_REGP_MSDC0_SLV_H 105 +#define CLK_INFRACFG_AO_REGP_MSDC1 106 +#define CLK_INFRACFG_AO_REGP_MSDC1_H 107 +#define CLK_INFRACFG_AO_REGP_MSDC1_MST_F 108 +#define CLK_INFRACFG_AO_REGP_MSDC1_SLV_H 109 +#define CLK_INFRACFG_AO_REGP_MSDC2 110 +#define CLK_INFRACFG_AO_REGP_MSDC2_H 111 +#define CLK_INFRACFG_AO_REGP_MSDC2_MST_F 112 +#define CLK_INFRACFG_AO_REGP_MSDC2_SLV_H 113 +#define CLK_INFRACFG_AO_REGP_SFLASH 114 +#define CLK_INFRACFG_AO_REGP_SFLASH_F 115 +#define CLK_INFRACFG_AO_REGP_SFLASH_H 116 +#define CLK_INFRACFG_AO_REGP_SFLASH_P 117 +#define CLK_INFRACFG_AO_REGP_BTIF_B 118 +#define CLK_INFRACFG_AO_REGP_CAN0_P 119 +#define CLK_INFRACFG_AO_REGP_CAN0 120 +#define CLK_INFRACFG_AO_REGP_NFI_H 121 +#define CLK_INFRACFG_AO_REGP_NFI_B 122 +#define CLK_INFRACFG_AO_REGP_NFIECC_B 123 + +/* IMP_IIC_WRAP_C */ +#define CLK_IMPC_I2C1 0 +#define CLK_IMPC_I2C2 1 +#define CLK_IMPC_I2C3 2 +#define CLK_IMPC_I2C5 3 +#define CLK_IMPC_I2C6 4 +#define CLK_IMPC_I2C7 5 +#define CLK_IMPC_I2C8 6 +#define CLK_IMPC_I2C9 7 + +/* IMP_IIC_WRAP_E */ +#define CLK_IMPE_I2C0 0 +#define CLK_IMPE_I2C4 1 + +/* DISPSYS_CONFIG */ +#define CLK_MM_DISP_OVL0_4L 0 +#define CLK_MM_DISP_OVL1_4L 1 +#define CLK_MM_DISP_RSZ0 2 +#define CLK_MM_DISP_RSZ1 3 +#define CLK_MM_DISP_RDMA0 4 +#define CLK_MM_DISP_RDMA1 5 +#define CLK_MM_DISP_COLOR1 6 +#define CLK_MM_DISP_CCORR1 7 +#define CLK_MM_DISP_CCORR3 8 +#define CLK_MM_DISP_AAL1 9 +#define CLK_MM_DISP_GAMMA1 10 +#define CLK_MM_DISP_DITHER1 11 +#define CLK_MM_VPP_MERGE0 12 +#define CLK_MM_DISP_DSI0_MM 13 +#define CLK_MM_DP_INTF0_MM 14 +#define CLK_MM_DPI0_MM 15 +#define CLK_MM_DISP_WDMA0 16 +#define CLK_MM_DISP_DSI1_MM 17 +#define CLK_MM_DISP_FAKE_ENG0 18 +#define CLK_MM_DISP_FAKE_ENG1 19 +#define CLK_MM_SMI_SUB_COMMON 20 +#define CLK_MM_DISP_MUTEX0 21 +#define CLK_MM_DISP_APB_BUS 22 +#define CLK_MM_LVDS_ENCODER 23 +#define CLK_MM_EPD_DLI_ASYNC 24 +#define CLK_MM_SMI 25 +#define CLK_MM_DISP_DSI0 26 +#define CLK_MM_DPI0 27 +#define CLK_MM_LVDS_ENCODER_PXL 28 +#define CLK_MM_DISP_DSI1 29 +#define CLK_MM_DP_INTF0 30 +#define CLK_MM_LVDS_ENCODER_CTS 31 +#define CLK_MM_AXI 32 +#define CLK_MM_EPDSYS 33 +#define CLK_MM_MM_CK_GLOBAL 34 +#define CLK_MM_DISP_DSI0_CK_GLOBAL 35 +#define CLK_MM_LVDS_PXL_CK_GLOBAL 36 +#define CLK_MM_DISP_DSI1_GLOBAL 37 +#define CLK_MM_DP_CK_GLOBAL 38 +#define CLK_MM_LVDS_CTS_CK_GLOBAL 39 +#define CLK_MM_AXI_CK_GLOBAL 40 +#define CLK_MM_EPDSYS_CK_GLOBAL 41 +#define CLK_MM_26M 42 +#define CLK_MM_32K 43 + +/* DPTX_PHYD_SIFSLV_DIG_GLB */ +#define CLK_DPTX_PHYD_SIFSLV_DIG_GLB_RG_REF_CK_ENA 0 + +/* EPDSYS_CONFIG */ +#define CLK_EPDSYS_PIPELINE_TOP 0 +#define CLK_EPDSYS_PIPELINE_IMAGE_RDMA 1 +#define CLK_EPDSYS_PIPELINE_WORKING_RDMA 2 +#define CLK_EPDSYS_PIPELINE_WDMA 3 +#define CLK_EPDSYS_PIPELINE_WF_LUT_TOP 4 +#define CLK_EPDSYS_PIPELINE_DPI 5 +#define CLK_EPDSYS_PIPELINE_6 6 +#define CLK_EPDSYS_PIPELINE_IMAGE_PROCESS 7 +#define CLK_EPDSYS_DISP_COLOR 8 +#define CLK_EPDSYS_DISP_CCORR 9 +#define CLK_EPDSYS_DPI 10 +#define CLK_EPDSYS_TCON 11 +#define CLK_EPDSYS_SMI_LARB3 12 +#define CLK_EPDSYS_SMI_LARB8 13 +#define CLK_EPDSYS_IMG_DL_RELAY 14 +#define CLK_EPDSYS_26M_HRTWT 15 +#define CLK_EPDSYS_DPI0_MM 16 + +/* VDEC_GCON_BASE */ +#define CLK_VDE2_LARB1_CKEN 0 +#define CLK_VDE2_LAT_CKEN 1 +#define CLK_VDE2_LAT_ACTIVE 2 +#define CLK_VDE2_LAT_CKEN_ENG 3 +#define CLK_VDE2_MINI_MDP_EN 4 +#define CLK_VDE2_VDEC_CKEN 5 +#define CLK_VDE2_VDEC_ACTIVE 6 +#define CLK_VDE2_VDEC_CKEN_ENG 7 + +/* IPE */ +#define CLK_IPE_LARB19 0 +#define CLK_IPE_LARB20 1 +#define CLK_IPE_SMI_SUBCOM 2 +#define CLK_IPE_FD 3 +#define CLK_IPE_FE 4 +#define CLK_IPE_RSC 5 +#define CLK_IPE_GALS 6 + +/* CAMSYS_MAIN */ +#define CLK_CAM_M_LARB13 0 +#define CLK_CAM_M_DFP_VAD 1 +#define CLK_CAM_M_LARB14 2 +#define CLK_CAM_M_CAM 3 +#define CLK_CAM_M_CAMTG 4 +#define CLK_CAM_M_SENINF 5 +#define CLK_CAM_M_CAMSV1 6 +#define CLK_CAM_M_CAMSV2 7 +#define CLK_CAM_M_CAMSV3 8 +#define CLK_CAM_M_CCU0 9 +#define CLK_CAM_M_CCU1 10 +#define CLK_CAM_M_MRAW0 11 +#define CLK_CAM_M_FAKE_ENG 12 +#define CLK_CAM_M_CCU_GALS 13 +#define CLK_CAM_M_CAM2MM_GALS 14 +#define CLK_CAM_M_CAMSV4 15 +#define CLK_CAM_M_PDA 16 + +#endif /* _DT_BINDINGS_CLK_MT8366_H */ -- 2.43.0