[PATCH v2 6/8] ARM: dts: r9a06g032: add QSPI controller
Ralph Siemsen <[email protected]>
| Newsgroups | org.u-boot-project.lists.u-boot |
|---|---|
| Message-ID | <[email protected]> |
The RZ/N1 has a Quad-SPI controller based on Cadence IP core.
Take the devicetree for it from linux v7.1-rc2 commit
5be0b48a3b23 ("ARM: dts: renesas: r9a06g032: Describe the QSPI controller"
Signed-off-by: Ralph Siemsen <[email protected]>
---
Changes in v2:
- update to exactly match linux-7.1 commit 5be0b48a3b23
- this means qspi driver needs a new compatible string added
---
arch/arm/dts/r9a06g032.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
index f4f760aff28..164d30c5388 100644
--- a/arch/arm/dts/r9a06g032.dtsi
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -66,6 +66,18 @@
#size-cells = <1>;
ranges;
+ qspi0: spi@40005000 {
+ compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi";
+ reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
+ <&sysctrl R9A06G032_HCLK_QSPI0>;
+ clock-names = "ref", "ahb", "apb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
rtc0: rtc@40006000 {
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
reg = <0x40006000 0x1000>;
--
2.55.0