Re: [PATCH v2 1/4] i2c: k1: fix wrong bus speed setting

> The controller bus mode should be selected according to the requested
> I2C bus speed. However, the driver currently passes the functional clock
> rate to k1_i2c_set_bus_speed(), so the selected mode does not reflect
> the requested bus speed.
>
> Fix this by reading the clock-frequency property from the Device Tree,
> defaulting to standard speed, and drop the unused clk_rate field.

`clock-frequency` is the requested SCL rate, but this patch only changes the
value passed to `k1_i2c_set_bus_speed()`.

> @@ -496,10 +496,13 @@ static int k1_i2c_probe(struct udevice *bus)
>  		debug("%s: failed to enable clock\n", __func__);
>  		return ret;
>  	}
> -	priv->clk_rate = clk_get_rate(&priv->clk);
>
>  	priv->base = (void *)devfdt_get_addr_ptr(bus);
> -	k1_i2c_set_bus_speed(bus, priv->clk_rate);
> +
> +	speed = dev_read_u32_default(bus, "clock-frequency",
> +				     I2C_SPEED_STANDARD_RATE);
> +	k1_i2c_set_bus_speed(bus, speed);

`k1_i2c_set_bus_speed()` only changes `ICR_MODE_MASK`. It does not program
the ILCR divider or initialize IWCR, so the actual SCL rate still depends on
the register reset values and may not match the Device Tree.

Please calculate and program ILCR from the functional clock rate and the
requested SCL rate, initialize IWCR as required by the hardware, and reject
unsupported rates. The functional clock handle or rate therefore needs to
remain available to `k1_i2c_set_bus_speed()`.

                                            - Troy

-----BEGIN PGP SIGNATURE-----

iIMEABYKACsWIQSL4Ay2cExaPXAQcU2YCe+A+TM0LwUCaoLQgw0caUB0cm95LXku
b3JnAAoJEJgJ74D5MzQvixQA/A3hj4lows2eyiVz53LXVkiaEyx6mr4XpYZMY0Rx
BeGEAQCB/DkZybfQQ/SgC30KkdDX1CPADpV6breky1Cok1AbDg==
=ezAM
-----END PGP SIGNATURE-----