Re: [PATCH 0/3] Semi-Falcon Boot Support

On Mon, Aug 17, 2026 at 01:46:10PM +0530, Gokul Praveen wrote:
> Hi Tom,
> 
> On 14/08/26 20:26, Tom Rini wrote:
> > On Fri, Aug 14, 2026 at 03:51:50PM +0530, Gokul Praveen wrote:
> > 
> > > Semi-Falcon Mode is a hybrid boot approach that bypasses
> > > the A72 SPL while retaining U-Boot in the boot flow. This mode provides faster
> > > boot times compared to normal boot while maintaining U-Boot's flexibility for
> > > kernel loading and system configuration..
> > > 
> > > Boot logs link :
> > > 
> > > https://gist.github.com/GokulPraveen2001/fef407a482e2dad30272006de557627c
> > > 
> > > Gokul Praveen (3):
> > >    configs: add semi-falcon mode fragment for k3 devices
> > >    arm: k3-binman: add tisemifalcon.bin for semi-falcon mode
> > >    doc: ti: document semi-falcon mode for J784S4 EVM
> > This is just doing what many other aarch64 platforms do, of skipping the
> > SPL phase in Cortex-A because something else has already done any
> > required initialization, unless I'm reading all of this wrong. So my
> > feedback is:
> > - It's not "semi-falcon", it's just "no SPL". Naming differences, if
> >    any, should be done with that in mind.
> 
> Actually, there is an SPL in Cortex-R5 which is still present in the
> semi-falcon bootflow.

Yes. But it's not "semi-falcon", at all, as "falcon" refers to booting
directly to Linux.

> Its only the Cortex-A SPL which is avoided, which is why I did not name it
> as "no SPL"
> 
> *Normal K3 Bootflow*: R5 SPL + TFA + OPTEE + DM + Cortex-A SPL + UBOOT +
> Kernel
> 
> *Semi-Falcon* *boot flow* is : R5 SPL + TFA + OPTEE + DM + UBOOT + Kernel

Yes, and this is similar to other platforms, where the Cortex-R or
similar isn't exposed in the same fashion as it is for TI.

> > - You should make sure to structure this so any K3 platform *could* take
> >    advantage. I seem to recall part of the rationale for the current
> >    approach is that some variants might only have a little SRAM (512k?
> >    256k?) while others might have 1-2M and so easily fit U-Boot in SRAM
> >    prior to relocation. It sounds like this specific family has a large
> >    enough lower memory bound.
> > 
> Yes, this is structured in a way that all K3 platforms can take advantage of
> this approach and changes.
> 
> Additionally, as there is an SPL running in cortex-R5 even with this
> bootflow(semi-falcon).
> 
> this bootflow can be used on all variants irrespective of whether they have
> less or more memory.

OK good. Just come up with a different way of describing this that
doesn't say "falcon", thanks.

-- 
Tom

-----BEGIN PGP SIGNATURE-----

iHUEABYKAB0WIQTzzqh0PWDgGS+bTHor4qD1Cr/kCgUCaoN7fwAKCRAr4qD1Cr/k
CgOyAQCBrXlklFYrHX2TsDgzS11Kda1zlEFvCnqSNUGLoBVSWQD+L1Q9KWFVhY38
m24/RYb7KCPqWf/ccKTjWcQd3FdscAg=
=i3XT
-----END PGP SIGNATURE-----