Re: [PATCH] pci: pcie_dw_rockchip: add PCIe reset configuration delay

Quentin Schulz <[email protected]> Fri, 21 Aug 2026 20:26:35 +0200

Newsgroups	org.u-boot-project.lists.u-boot
Message-ID	<[email protected]>

Hi Oleg,

On 8/14/26 3:42 PM, Oleg Kombarov via B4 Relay wrote:
> From: Oleg Kombarov <[email protected]>
> 
> PCIe r6.0 sec 6.6.1 requires a 100 ms delay before the first
> Configuration Request.
> 
> For ports supporting up to 5.0 GT/s, the delay is measured from
> the end of Conventional Reset. For faster ports, it is measured
> from the end of Link Training.
> 

Could you please explain why they should be handled differently?

Cheers,
Quentin