[PATCH] clk: clk-uclass: Ignore -ENOSYS in clk_set_default_rates()

clk_set_default_parents() already ignores -ENOSYS from clk_set_parent().
Do the same for clk_set_default_rates() and rely on the earlier setup
clock rates.

On am437x the cpsw switch has assigned-clock-rates for the RGMII clock.
The divider delegates to a multiplier of the DPLL that has no set_rate
and no delegation, so it returns -ENOSYS.

Signed-off-by: Markus Schneider-Pargmann (TI) <[email protected]>
---
 drivers/clk/clk-uclass.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index c33f415917e9..0069ce9a8875 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -359,6 +359,15 @@ static int clk_set_default_rates(struct udevice *dev,
 
 		ret = clk_set_rate(c, rates[index]);
 
+		/*
+		 * Not all drivers/clocks support setting the rate (as of now).
+		 * Ignore that and keep the rate set by an earlier boot stage.
+		 */
+		if (ret == -ENOSYS) {
+			ret = 0;
+			continue;
+		}
+
 		if (IS_ERR_VALUE(ret)) {
 			dev_warn(dev,
 				 "failed to set rate on clock index %d (%ld) (error = %d)\n",

---
base-commit: d3e8597e46b635ec556a057bc42f0b0859654bdf
change-id: 20260827-v2026-10-next-topic-am45-ofupstream-clk-default-rates-enosys-1359deb9d80b

Best regards,
--  
Markus Schneider-Pargmann (TI) <[email protected]>