Re: IBM - New SUB-Nanometer STACKED Chip

On 6/30/26 19:28, rbowman wrote:
> On Tue, 30 Jun 2026 16:27:24 +0100, The Natural Philosopher wrote:
> 
>> "Transistor nodes have shrunk dramatically, with leading developers like
>> IBM advancing into the sub-1 nanometre realm (e.g., 0.7-nanometer tech).
>> However, absolute limits are rapidly approaching due to several factors:
> 
> iirc terms like '5 nm process' no longer refer to any physical dimension
> so I'm curious what the actual gate size is on 0.7 nm tech.
> 
> IBM sold their fab lines to GlobalFoundries and their '7 nm' tech was
> closer to Intel's 10 nm.

   Well, SEEMS like they've done the 1, or <1, nm
   stacked chip.

   They'll license that. Old company, but still kinda
   out-front in their tech AND biz sense. NOT gonna
   dump my stock.

   Alas, as mentioned here, this IS about as far as
   conventional electronics can go. Under 1nm the
   quantum issues fuck up everything.

   SO - we need entirely new tech paradigms now.
   For 'electronics' we HAVE crashed into Dr. Moore.

   Meanwhile, the stacked chips DO allow us to do
   more, if not faster, in the same chip profiles.
   There's money in that - for now.

   Five years ... as said, we need Something Completely
   Different. Maybe I'll be dead by then and won't care,
   maybe not, but "transistors" aren't gonna go any
   faster even as "AI" and a lot more DEMAND that.

   Still wonder if "deca-state" logic, where the
   intermediate values are stable and DON'T eat up
   power, can be done. Some 'latching', 'layered',
   design maybe. A few more layers per transistor.
   I have this vague vision in my head ... quantified
   analog, so to speak. One transistor, 2^10th
   possible values.