[PATCH 6/6] rockchip: rk3506: Use FIELD_PREP_WM16 macro

Change to use writel() together with the FIELD_PREP_WM16() macro instead
of using the rk_clrreg() macro or custom write-enable bit handling.

No change in behavior is expected due to this code style change.

Signed-off-by: Jonas Karlman <[email protected]>
---
 arch/arm/mach-rockchip/rk3506/rk3506.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3506/rk3506.c b/arch/arm/mach-rockchip/rk3506/rk3506.c
index 2ed1dcc128e0..ef0943434e5e 100644
--- a/arch/arm/mach-rockchip/rk3506/rk3506.c
+++ b/arch/arm/mach-rockchip/rk3506/rk3506.c
@@ -6,7 +6,8 @@
 #include <dm.h>
 #include <misc.h>
 #include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <linux/hw_bitfield.h>
 
 #define SGRF_BASE			0xff210000
 
@@ -32,7 +33,7 @@ int arch_cpu_init(void)
 		return 0;
 
 	/* Select non-secure OTPC */
-	rk_clrreg(SGRF_BASE + 0x100, BIT(1));
+	writel(FIELD_PREP_WM16(BIT(1), 0), SGRF_BASE + 0x0100);
 
 	/* Set the sdmmc/emmc to access ddr memory */
 	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
@@ -77,7 +78,7 @@ void rockchip_stimer_init(void)
 	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (CONFIG_COUNTER_FREQUENCY));
 	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
 	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
-	writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
+	writel(FIELD_PREP_WM16(TIMER_EN, 1), HP_TIMER_BASE + HP_CTRL_REG);
 }
 
 #define RK3506_OTP_CPU_CODE_OFFSET		0x02
-- 
2.54.0