Re: Bug in VHDL generation (6.08) with candidate patch

>This VHDL causes the silicon compiler to barf (SEGV);
>
>....
>The "Do Placement" command pops a dialog stating FATAL ERROR: A
>segmentation violation has occurred.
>
>Is this a known issue with Electric? Any fix or workaround?

The problem here is that you have a very simple circuit, but the default 
setting in the silicon compiler is to create 4 rows of standard cells.  You 
don't even have 4 cells to place!  If you set the Silicon Compiler Options 
to create 1 row instead of 4, it will work.

I realize that it should handle the situation more gracefully than 
crashing, and I will look into that problem separately.

>Electric 6.08 generates incorrect VHDL for XNOR2. I later discovered that
>the CMOS library doesn't have a pattern for XNOR, so this is probably
>something of a non-issue to most people. But I attach a patch for this
>anyway...

Thanks for your patch.  I have incorporated it into the next release of 
Electric.

    -Steven Rubin