Re: Bug in VHDL generation (6.08) with candidate patch

On Thu, 17 Jul 2003, Steven Rubin wrote:
>
> The problem here is that you have a very simple circuit, but the default
> setting in the silicon compiler is to create 4 rows of standard cells.  You
> don't even have 4 cells to place!  If you set the Silicon Compiler Options
> to create 1 row instead of 4, it will work.

Ah! Silly me! Indeed, I noticed it appears to work in a larger circuit.
Sorry if that is documented somewhere.

/.J