Re: Question about layers in Electric

At 12:54 PM 6/27/2011, you wrote:
>Hi,
>
>I am currently working on several layouts that involve 
>enclosed-layout transistors and guard rings. I was trying to put a 
>p-doped ring around the n-channel transistors, however, the tool 
>places an n-well around the p-active layer when I place it. I was 
>wondering if there was a way to use the p-active layer without the 
>n-well being automatically placed around it. I was also unsure of 
>the difference between "p-active nodes" and "p-active-well-nodes" in 
>the mocmos technology. If anyone could help, I would really appreciate it.

The transistors in the MOSIS CMOS technology are able to fabricated 
in n-well or p-well processes, because each one has both an "n" and a 
"p" component.  P transistors have N-well and P-select around them, N 
transistors have P-well and N-select around them.  It is sometimes 
the case that half of these layers are ignored, depending on the process.

It sounds like you want something completely different: a guard ring 
made from some other layer.  Depending on the layer you need, it may 
be available in the technology and able to be placed with "pure layer 
nodes".  You can then encapsulate the transistor and the necessary 
ring into a subcell and then use it instead of a transistor.

As far as the difference between p-active and p-active-well, both are 
just "diffusion" layers, but the former is regular "active" and the 
later is something used in special nodes, where a distinction must be 
made at the foundry.

    -Steven Rubin