Re: RC5 with FPGAs

What one could do, is to reverse engineer the buffer format, and then use a
normal dnetc client to submit the workunits.



On 5/16/06, [email protected] <[email protected]> wrote:
>
> Hello,
>
> I hope I will have more echoes using the hardware mailing list.
>
> I'm Guerric Meurice de Dormale and I'm a Ph.D. Student at the
> UCL CryptoGroup (Belgium) under the supervision of Jean-Jacques
> Quisquater.
> One of our Ms.C. Student is currently finishing the implementation the
> RC5 32/12/9 challenge on an FPGA platform. It is a fully pipelined design
> with a throughput of one key search every clock cycle.
> Currently, the engine should goes up to 150M keys/sec on a Xilinx
> VirtexII6000-5 device. In the future, it is planned to use Virtex4LX
> FPGAs with a higher logic density and a higher maximum operating
> frequency (a twofold improvement about the frequency is expected (?)).
>
> It could be very valuable for the work of our student to join the
> distributed.net cracking effort. However, as the communication
> protocol is not available, it is not possible without your support.
> Nevertheless, it seems that people were planning to enable FPGA engine
> within the key search effort (cfr. Hardware mailing list). Does
> someone know if something was done in that area? or if something could be
> done?
>
> I already thank you for reading this email.
> I hope we could join distributed.net soon!
>
> --
> Best regards,
> Guerric Meurice de Dormale
> Ph.D. Student
> UCL DICE/Crypto Group
> http://www.dice.ucl.ac.be/crypto/
>
>
> _______________________________________________
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> Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected]
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>



-- 
FIN|ACK

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