Re: RC5 with FPGAs
Fugu <[email protected]> Wed, 14 Jun 2006 15:13:04 -0600
| Newsgroups | gmane.comp.distributed-net.hardware |
|---|---|
| Message-ID | <[email protected]> |
One could do hardware error detection by re-encrypting the "decrypted" message by the same key, and comparing it to the given message. On 5/30/06, Jim C. Nasby <[email protected]> wrote: > On Tue, May 16, 2006 at 06:26:01PM +0200, [email protected] wrote: > > Hello, > > > > I hope I will have more echoes using the hardware mailing list. > > Unfortunately, all the lists were offline for the past several weeks. :( > > > I'm Guerric Meurice de Dormale and I'm a Ph.D. Student at the > > UCL CryptoGroup (Belgium) under the supervision of Jean-Jacques > > Quisquater. > > One of our Ms.C. Student is currently finishing the implementation the > > RC5 32/12/9 challenge on an FPGA platform. It is a fully pipelined design > > with a throughput of one key search every clock cycle. > > Currently, the engine should goes up to 150M keys/sec on a Xilinx > > VirtexII6000-5 device. In the future, it is planned to use Virtex4LX > > FPGAs with a higher logic density and a higher maximum operating > > frequency (a twofold improvement about the frequency is expected (?)). > > That would be outstanding. :) > > > It could be very valuable for the work of our student to join the > > distributed.net cracking effort. However, as the communication > > protocol is not available, it is not possible without your support. > > Nevertheless, it seems that people were planning to enable FPGA engine > > within the key search effort (cfr. Hardware mailing list). Does > > someone know if something was done in that area? or if something could be > > done? > > Probably the best bet would be for all the relevant parties to sign NDAs > so that we can provide you with the encryption protocol. I'd love to see > a means to talk to FPGA's more genericly, but I'm at a loss for how to > do that without creating some rather serious security issues for us. > > Speaking of security, the clients also compute a residual value (a CMC) > that is verified by the master. Ideally, the FPGA would also handle > this, but I'm not sure if it's that simple. > -- > Jim C. Nasby, Database Architect [email protected] > Give your computer some brain candy! www.distributed.net Team #1828 > > Windows: "Where do you want to go today?" > Linux: "Where do you want to go tomorrow?" > FreeBSD: "Are you guys coming, or what?" > _______________________________________________ > Hardware mailing list > Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected] > http://lists.distributed.net/mailman/listinfo/hardware > -- FIN|ACK _______________________________________________ Hardware mailing list Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected] http://lists.distributed.net/mailman/listinfo/hardware