Re: "success"

Well, how is the data verified and sent back? (conceptually, I'm not 
looking for details)
There could always be some sort of software layer on a host computer 
with any number of client FPGAs attached.

By the way, I made a simple top module and tried to synthesize the code 
today. It started to work but I tried to re-run the synthesis and 
Synplify Pro just sat there for hours running 100%. I'm not sure what's 
going on with that - maybe it just needs a reboot. I don't know how much 
space it will take up in an FPGA. It's a 155 stage 32 bit pipeline which 
seems large by my standards. It is for this reason that I don't know 
which device it will fit in (I use Xilinx S3-200 right now) or how fast 
it will run.

I will give out the code once I figure out if there are any reasons not 
to do so. It's basically the code I posted to this list 10 months ago 
converted to Verilog and printed out with tac. It's also part of my 
graduate thesis.

IMO the reward for breaking 72 bit encryption should be $100k
--
Martin K


John L. Bass wrote:
> 	Out of curiosity... is there any way to safely embed our encrypt/decrypt
> 	functions in that code without it becomming public? Otherwise I'm not
> 	sure how we'd be able to plug one of these in to the network...
>
> The answer is still effectively no. There would have to be a standard
> hardware configuration to freeze it. Or at least a fixed set of cores
> for every usable FPGA, which at least in the beginning would require
> releasing the crypto to a half dozen or better FPGA developers (most
> of the FPGA RC5 user community).
>
> 	On Wed, Oct 18, 2006 at 12:55:32PM -0600, Olivier Meyer wrote:
> 	> >I just thought I'd let you guys know since this seems to be a 4 msgs a
> 	> >year mailing list :-)
>
> Which is why this list is dead. The proprietary interests block open
> access.
>
> John
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