Re: "success"
"Jim C. Nasby" <[email protected]> Wed, 18 Oct 2006 17:59:50 -0500
| Newsgroups | gmane.comp.distributed-net.hardware |
|---|---|
| Message-ID | <[email protected]> |
On Wed, Oct 18, 2006 at 06:54:02PM -0400, Martin Klingensmith wrote: > Well, how is the data verified and sent back? (conceptually, I'm not > looking for details) > There could always be some sort of software layer on a host computer > with any number of client FPGAs attached. There's a residual that's computed as part of the normal clients, and the server checks that. The issue with having a host machine do the encryption is that the decrypted data is then available for anyone to muck with. > By the way, I made a simple top module and tried to synthesize the code > today. It started to work but I tried to re-run the synthesis and > Synplify Pro just sat there for hours running 100%. I'm not sure what's > going on with that - maybe it just needs a reboot. I don't know how much > space it will take up in an FPGA. It's a 155 stage 32 bit pipeline which > seems large by my standards. It is for this reason that I don't know > which device it will fit in (I use Xilinx S3-200 right now) or how fast > it will run. > > I will give out the code once I figure out if there are any reasons not > to do so. It's basically the code I posted to this list 10 months ago > converted to Verilog and printed out with tac. It's also part of my > graduate thesis. > > IMO the reward for breaking 72 bit encryption should be $100k > -- > Martin K > > > John L. Bass wrote: > > Out of curiosity... is there any way to safely embed our encrypt/decrypt > > functions in that code without it becomming public? Otherwise I'm not > > sure how we'd be able to plug one of these in to the network... > > > > The answer is still effectively no. There would have to be a standard > > hardware configuration to freeze it. Or at least a fixed set of cores > > for every usable FPGA, which at least in the beginning would require > > releasing the crypto to a half dozen or better FPGA developers (most > > of the FPGA RC5 user community). > > > > On Wed, Oct 18, 2006 at 12:55:32PM -0600, Olivier Meyer wrote: > > > >I just thought I'd let you guys know since this seems to be a 4 msgs a > > > >year mailing list :-) > > > > Which is why this list is dead. The proprietary interests block open > > access. > > > > John > > _______________________________________________ > > Hardware mailing list > > Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected] > > http://lists.distributed.net/mailman/listinfo/hardware > > > _______________________________________________ > Hardware mailing list > Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected] > http://lists.distributed.net/mailman/listinfo/hardware > -- Jim C. Nasby, Database Architect [email protected] Give your computer some brain candy! www.distributed.net Team #1828 Windows: "Where do you want to go today?" Linux: "Where do you want to go tomorrow?" FreeBSD: "Are you guys coming, or what?" _______________________________________________ Hardware mailing list Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected] http://lists.distributed.net/mailman/listinfo/hardware