Re: The market of ASICs (One GigaKey / Second?) [Repost]

Hi Martin,

Didn't expect you did, it wasn't neat enough to have been produced
automatically with a script. There have been times when I too have
hacked the output of this with VI or SED because it was faster than
debugging changes to the C and Perl generators that I normally use.

I simply reposted the generator because this design style is very
useful for unrolling software loops into hardware designs, and a
variant of it is what produced the code segments posted Dec 25th
last year.

There is another (much larger) variant of it which produced the
pipelined VHDL versions of the design, along with tags for placement
that kept crashing XST. It's really nasty to have to generate
precise netlists with LOC for the entire design to get reasonable
place and route.

Good luck with your thesis :)

Have fun,
John


	John,
	I didn't use your code generator. It was all manual labor unfortunately.
	--
	Martin K

	John L. Bass wrote:
	> As you might note from Martin's post, this easily generates verilog with minor changes.
	>
	> Have fun!
	> John
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