Re: "success"

Sorry, wrong "from" adress

This is a forwarded message
From: Guerric Meurice de Dormale <[email protected]>
To: Hardware <hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected]>
Date: Thursday, October 19, 2006, 4:23:06 PM
Subject: [Hardware] "success"

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Hello,

Ok, I guess everything is clear between you and John now.

Talking about devices, if the biggest device you "can" (afford) work
with is a Spartan3E, there is maximum 14.5 kSlices and 36 bRAMS.
>From my point of view, it is not possible to fit a fully unrolled RC5
core with such amount of slices. (or I will be very happy to know
how!).
For such kind of devices, a partially unrolled core should probably be
the best solution (with let's say 3 key schedule stages and 1 decrypt
stage).

I'm not only saying that as I'm working on fully unrolled core and
with bigger FPGA: we worked on the problem during the first half of
the year and I really can't figure out how to reduce further our
~17500 slices. I'm currently adding other optimizations, but only a
couple of hundred slices are going to be saved.

Does a partially unrolled core can fit with the schedule of your work
? (I'm not saying you to do that, just thinking about what's
possible)

-- 
Guerric Meurice de Dormale
UCL DICE/Crypto Group
http://www.dice.ucl.ac.be/crypto/

MK> David,
MK> It is too large for the largest device I can afford, a Spartan 3E - 1600
MK> on board at Digilentinc.com
MK> There are larger Spartan 3 chips but I don't know of any on eval boards.
MK> Estimated frequency based on Synplify Pro for a Spartan 3 is 63MHz - not
MK> that impressive
MK> Virtex 4 - 127MHz
MK> As Mr. Bass pointed out, there are issues with a pipeline delay that I
MK> haven't figured out yet.
MK> --
MK> Martin K

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