[gcc r17-2799] RISC-V: Add test cases for vwsub.wv reg overlap
Pan Li via Gcc-cvs <[email protected]> Thu, 30 Jul 2026 00:56:04 +0000 (GMT)
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://gcc.gnu.org/g:a60b78ed3a53b71d551b1fe2111c561713ad482d commit r17-2799-ga60b78ed3a53b71d551b1fe2111c561713ad482d Author: Pan Li <[email protected]> Date: Mon Jul 27 15:48:52 2026 +0800 RISC-V: Add test cases for vwsub.wv reg overlap Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf8.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vwsub_wv-i16-m1.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i16-m2.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i16-m4.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i16-mf2.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i16-mf4.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i32-m1.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i32-m2.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i32-m4.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i32-mf2.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i8-m1.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i8-m2.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i8-m4.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i8-mf2.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i8-mf4.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsub_wv-i8-mf8.c | 32 ++++++++++++++++++++++ 15 files changed, 354 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m1.c new file mode 100644 index 000000000000..1a12fc6b471f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m1, + vint16m1_t, + vint32m2_t, + __riscv_vle16_v_i16m1, + __riscv_vle32_v_i32m2, + __riscv_vwsub_wv_i32m2, + __riscv_vse32_v_i32m2, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v2,v2,v25} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m2.c new file mode 100644 index 000000000000..a626ad64a3ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m2, + vint16m2_t, + vint32m4_t, + __riscv_vle16_v_i16m2, + __riscv_vle32_v_i32m4, + __riscv_vwsub_wv_i32m4, + __riscv_vse32_v_i32m4, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v8,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v16,v16,v0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m4.c new file mode 100644 index 000000000000..cebca68a7624 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m4, + vint16m4_t, + vint32m8_t, + __riscv_vle16_v_i16m4, + __riscv_vle32_v_i32m8, + __riscv_vwsub_wv_i32m8, + __riscv_vse32_v_i32m8, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v0,v12} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v8,v8,v28} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf2.c new file mode 100644 index 000000000000..f77dbcb82987 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m1, + vint16mf2_t, + vint32m1_t, + __riscv_vle16_v_i16mf2, + __riscv_vle32_v_i32m1, + __riscv_vwsub_wv_i32m1, + __riscv_vse32_v_i32m1, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf4.c new file mode 100644 index 000000000000..307463fd937c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i16-mf4.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m1, + vint16mf4_t, + vint32mf2_t, + __riscv_vle16_v_i16mf4, + __riscv_vle32_v_i32mf2, + __riscv_vwsub_wv_i32mf2, + __riscv_vse32_v_i32mf2, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m1.c new file mode 100644 index 000000000000..048047d65993 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m1, + vint32m1_t, + vint64m2_t, + __riscv_vle32_v_i32m1, + __riscv_vle64_v_i64m2, + __riscv_vwsub_wv_i64m2, + __riscv_vse64_v_i64m2, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v2,v2,v25} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m2.c new file mode 100644 index 000000000000..edf7b535b0bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m2, + vint32m2_t, + vint64m4_t, + __riscv_vle32_v_i32m2, + __riscv_vle64_v_i64m4, + __riscv_vwsub_wv_i64m4, + __riscv_vse64_v_i64m4, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v8,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v16,v16,v0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m4.c new file mode 100644 index 000000000000..6f8479347b8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m4, + vint32m4_t, + vint64m8_t, + __riscv_vle32_v_i32m4, + __riscv_vle64_v_i64m8, + __riscv_vwsub_wv_i64m8, + __riscv_vse64_v_i64m8, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v0,v12} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v8,v8,v28} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-mf2.c new file mode 100644 index 000000000000..a9d3d56ccb3f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i32-mf2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m1, + vint32mf2_t, + vint64m1_t, + __riscv_vle32_v_i32mf2, + __riscv_vle64_v_i64m1, + __riscv_vwsub_wv_i64m1, + __riscv_vse64_v_i64m1, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m1.c new file mode 100644 index 000000000000..66e62b500be1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vint8m1_t, + vint16m2_t, + __riscv_vle8_v_i8m1, + __riscv_vle16_v_i16m2, + __riscv_vwsub_wv_i16m2, + __riscv_vse16_v_i16m2, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v2,v2,v25} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m2.c new file mode 100644 index 000000000000..1b57f9158d47 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m2, + vint8m2_t, + vint16m4_t, + __riscv_vle8_v_i8m2, + __riscv_vle16_v_i16m4, + __riscv_vwsub_wv_i16m4, + __riscv_vse16_v_i16m4, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v8,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v16,v16,v0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m4.c new file mode 100644 index 000000000000..80a0fc507ac4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m4, + vint8m4_t, + vint16m8_t, + __riscv_vle8_v_i8m4, + __riscv_vle16_v_i16m8, + __riscv_vwsub_wv_i16m8, + __riscv_vse16_v_i16m8, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v0,v0,v12} 1 } } */ +/* { dg-final { scan-assembler-times {vwsub\.wv\s+v8,v8,v28} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf2.c new file mode 100644 index 000000000000..8a27a8a1b866 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vint8mf2_t, + vint16m1_t, + __riscv_vle8_v_i8mf2, + __riscv_vle16_v_i16m1, + __riscv_vwsub_wv_i16m1, + __riscv_vse16_v_i16m1, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf4.c new file mode 100644 index 000000000000..674c5f93bdd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf4.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vint8mf4_t, + vint16mf2_t, + __riscv_vle8_v_i8mf4, + __riscv_vle16_v_i16mf2, + __riscv_vwsub_wv_i16mf2, + __riscv_vse16_v_i16mf2, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf8.c new file mode 100644 index 000000000000..96234531ebf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_wv-i8-mf8.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vint8mf8_t, + vint16mf4_t, + __riscv_vle8_v_i8mf8, + __riscv_vle16_v_i16mf4, + __riscv_vwsub_wv_i16mf4, + __riscv_vse16_v_i16mf4, + vwsub_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsub\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */