[gcc r17-2800] RISC-V: Add test cases for vwsubu.wv reg overlap
Pan Li via Gcc-cvs <[email protected]> Thu, 30 Jul 2026 00:56:09 +0000 (GMT)
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
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https://gcc.gnu.org/g:865eff56437c52d9f94a20074a354185621847bd commit r17-2800-g865eff56437c52d9f94a20074a354185621847bd Author: Pan Li <[email protected]> Date: Mon Jul 27 15:49:10 2026 +0800 RISC-V: Add test cases for vwsubu.wv reg overlap Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf8.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vwsubu_wv-u16-m1.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u16-m2.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u16-m4.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u16-mf2.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u16-mf4.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u32-m1.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u32-m2.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u32-m4.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u32-mf2.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u8-m1.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u8-m2.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u8-m4.c | 18 ++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u8-mf2.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u8-mf4.c | 32 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vwsubu_wv-u8-mf8.c | 32 ++++++++++++++++++++++ 15 files changed, 354 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m1.c new file mode 100644 index 000000000000..9a41d417fd3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m1, + vuint16m1_t, + vuint32m2_t, + __riscv_vle16_v_u16m1, + __riscv_vle32_v_u32m2, + __riscv_vwsubu_wv_u32m2, + __riscv_vse32_v_u32m2, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v2,v2,v25} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m2.c new file mode 100644 index 000000000000..9c1e399aa768 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m2, + vuint16m2_t, + vuint32m4_t, + __riscv_vle16_v_u16m2, + __riscv_vle32_v_u32m4, + __riscv_vwsubu_wv_u32m4, + __riscv_vse32_v_u32m4, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v8,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v16,v16,v0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m4.c new file mode 100644 index 000000000000..7ba8c3aa797e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m4, + vuint16m4_t, + vuint32m8_t, + __riscv_vle16_v_u16m4, + __riscv_vle32_v_u32m8, + __riscv_vwsubu_wv_u32m8, + __riscv_vse32_v_u32m8, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v0,v12} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v8,v8,v28} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf2.c new file mode 100644 index 000000000000..f842cd281853 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf2_t, + vuint32m1_t, + __riscv_vle16_v_u16mf2, + __riscv_vle32_v_u32m1, + __riscv_vwsubu_wv_u32m1, + __riscv_vse32_v_u32m1, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf4.c new file mode 100644 index 000000000000..16986dfdc5cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u16-mf4.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf4_t, + vuint32mf2_t, + __riscv_vle16_v_u16mf4, + __riscv_vle32_v_u32mf2, + __riscv_vwsubu_wv_u32mf2, + __riscv_vse32_v_u32mf2, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m1.c new file mode 100644 index 000000000000..d8a0fd428566 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m1, + vuint32m1_t, + vuint64m2_t, + __riscv_vle32_v_u32m1, + __riscv_vle64_v_u64m2, + __riscv_vwsubu_wv_u64m2, + __riscv_vse64_v_u64m2, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v2,v2,v25} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m2.c new file mode 100644 index 000000000000..06a5f520cd15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m2, + vuint32m2_t, + vuint64m4_t, + __riscv_vle32_v_u32m2, + __riscv_vle64_v_u64m4, + __riscv_vwsubu_wv_u64m4, + __riscv_vse64_v_u64m4, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v8,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v16,v16,v0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m4.c new file mode 100644 index 000000000000..b3ca3ae08bd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m4, + vuint32m4_t, + vuint64m8_t, + __riscv_vle32_v_u32m4, + __riscv_vle64_v_u64m8, + __riscv_vwsubu_wv_u64m8, + __riscv_vse64_v_u64m8, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v0,v12} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v8,v8,v28} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-mf2.c new file mode 100644 index 000000000000..3332f55c76b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u32-mf2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e32m1, + vuint32mf2_t, + vuint64m1_t, + __riscv_vle32_v_u32mf2, + __riscv_vle64_v_u64m1, + __riscv_vwsubu_wv_u64m1, + __riscv_vse64_v_u64m1, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m1.c new file mode 100644 index 000000000000..5613fccb4c06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vuint8m1_t, + vuint16m2_t, + __riscv_vle8_v_u8m1, + __riscv_vle16_v_u16m2, + __riscv_vwsubu_wv_u16m2, + __riscv_vse16_v_u16m2, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v4,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v2,v2,v25} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m2.c new file mode 100644 index 000000000000..24e80cb95775 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m2, + vuint8m2_t, + vuint16m4_t, + __riscv_vle8_v_u8m2, + __riscv_vle16_v_u16m4, + __riscv_vwsubu_wv_u16m4, + __riscv_vse16_v_u16m4, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v8,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v16,v16,v0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m4.c new file mode 100644 index 000000000000..b18bb869ddf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-m4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m4, + vuint8m4_t, + vuint16m8_t, + __riscv_vle8_v_u8m4, + __riscv_vle16_v_u16m8, + __riscv_vwsubu_wv_u16m8, + __riscv_vse16_v_u16m8, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v0,v0,v12} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu\.wv\s+v8,v8,v28} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf2.c new file mode 100644 index 000000000000..ef882a7034e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf2_t, + vuint16m1_t, + __riscv_vle8_v_u8mf2, + __riscv_vle16_v_u16m1, + __riscv_vwsubu_wv_u16m1, + __riscv_vse16_v_u16m1, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf4.c new file mode 100644 index 000000000000..dc6f567916b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf4.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf4_t, + vuint16mf2_t, + __riscv_vle8_v_u8mf4, + __riscv_vle16_v_u16mf2, + __riscv_vwsubu_wv_u16mf2, + __riscv_vse16_v_u16mf2, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf8.c new file mode 100644 index 000000000000..267c96d64798 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_wv-u8-mf8.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf8_t, + vuint16mf4_t, + __riscv_vle8_v_u8mf8, + __riscv_vle16_v_u16mf4, + __riscv_vwsubu_wv_u16mf4, + __riscv_vse16_v_u16mf4, + vwsubu_wv, + LOOP_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v0,v[0-9]+,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v2,v[0-9]+,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v4,v[0-9]+,v5([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v6,v[0-9]+,v7([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v8,v[0-9]+,v9([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v10,v[0-9]+,v11([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v12,v[0-9]+,v13([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v14,v[0-9]+,v15([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v16,v[0-9]+,v17([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v18,v[0-9]+,v19([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v20,v[0-9]+,v21([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v22,v[0-9]+,v23([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v24,v[0-9]+,v25([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v26,v[0-9]+,v27([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v28,v[0-9]+,v29([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vwsubu\.wv\s+v30,v[0-9]+,v31([^0-9]|$)} } } */