[gcc r17-2867] RISC-V: Allow RVV register overlap for vw{add, sub, mul}[u].vv

https://gcc.gnu.org/g:322ba88ffa340d841755eedd76f0f03978b77b71

commit r17-2867-g322ba88ffa340d841755eedd76f0f03978b77b71
Author: Pan Li <[email protected]>
Date:   Thu Jul 30 15:36:00 2026 +0800

    RISC-V: Allow RVV register overlap for vw{add,sub,mul}[u].vv
    
    Like vwadd[u].wv, allow the rvv register overlap for the dual
    widen vv insns, aka vwadd[u].vv, vwsub[u].vv and vwmul[u].vv.
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Leverage Wvr constraint.
    
    Signed-off-by: Pan Li <[email protected]>
    Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>

Diff:
---
 gcc/config/riscv/vector.md | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 04684c458a73..afaa3a51ece2 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4150,22 +4150,22 @@
 
 ;; Vector Widening Add/Subtract/Multiply.
 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vr, vr, vd, vd")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
-	     (match_operand 5 "vector_length_operand"              "  rvl,  rvl")
-	     (match_operand 6 "const_int_operand"                  "    i,    i")
-	     (match_operand 7 "const_int_operand"                  "    i,    i")
-	     (match_operand 8 "const_int_operand"                  "    i,    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "Wc1,Wc1, vm, vm")
+	     (match_operand 5 "vector_length_operand"              "rvl,rvl,rvl,rvl")
+	     (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"                  "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_widen_binop:VWEXTI
 	    (any_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
+	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "Wvr,Wvr,Wvr,Wvr"))
 	    (any_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
+	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr,Wvr,Wvr")))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")