[gcc r17-2868] RISC-V: Add test cases for vwadd.vv reg overlap
Pan Li via Gcc-cvs <[email protected]> Sat, 1 Aug 2026 07:13:52 +0000 (GMT)
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
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https://gcc.gnu.org/g:5f56bb4184dbaddcb625c8457b192305fadc3c7a commit r17-2868-g5f56bb4184dbaddcb625c8457b192305fadc3c7a Author: Pan Li <[email protected]> Date: Thu Jul 30 15:36:21 2026 +0800 RISC-V: Add test cases for vwadd.vv reg overlap Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf8.c: New test. Signed-off-by: Pan Li <[email protected]> Co-Authored-By: Claude Opus 5 (1M context) <[email protected]> Diff: --- .../rvv/autovec/group_overlap/group_overlap.h | 154 +++++++++++++++++++++ .../rvv/autovec/group_overlap/vwadd_vv-i16-m1.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i16-m2.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i16-m4.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i16-mf2.c | 19 +++ .../rvv/autovec/group_overlap/vwadd_vv-i16-mf4.c | 19 +++ .../rvv/autovec/group_overlap/vwadd_vv-i32-m1.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i32-m2.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i32-m4.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i32-mf2.c | 19 +++ .../rvv/autovec/group_overlap/vwadd_vv-i8-m1.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i8-m2.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i8-m4.c | 17 +++ .../rvv/autovec/group_overlap/vwadd_vv-i8-mf2.c | 19 +++ .../rvv/autovec/group_overlap/vwadd_vv-i8-mf4.c | 19 +++ .../rvv/autovec/group_overlap/vwadd_vv-i8-mf8.c | 19 +++ 16 files changed, 421 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h index d3f0943032a9..647622cae5a0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h @@ -252,6 +252,145 @@ ST_F ((void *)out, vd14, VL); OUT += VL; \ ST_F ((void *)out, vd15, VL); OUT += VL; \ +#define LOOP_DUAL_WIDEN_BINARY_BODY_X4(NT, WT, LD_NF, OUT_F, ST_F, OUT, \ + START, VL) \ + NT vs0 = LD_NF ((void *)START, VL); START += VL; \ + NT vs1 = LD_NF ((void *)START, VL); START += VL; \ + NT vs2 = LD_NF ((void *)START, VL); START += VL; \ + NT vs3 = LD_NF ((void *)START, VL); START += VL; \ + NT vt0 = LD_NF ((void *)START, VL); START += VL; \ + NT vt1 = LD_NF ((void *)START, VL); START += VL; \ + NT vt2 = LD_NF ((void *)START, VL); START += VL; \ + NT vt3 = LD_NF ((void *)START, VL); START += VL; \ + \ + asm volatile("nop" ::: "memory"); \ + \ + WT vd0 = OUT_F (vs0, vt0, VL); \ + WT vd1 = OUT_F (vs1, vt1, VL); \ + WT vd2 = OUT_F (vs2, vt2, VL); \ + WT vd3 = OUT_F (vs3, vt3, VL); \ + \ + asm volatile("nop" ::: "memory"); \ + \ + ST_F ((void *)out, vd0, VL); OUT += VL; \ + ST_F ((void *)out, vd1, VL); OUT += VL; \ + ST_F ((void *)out, vd2, VL); OUT += VL; \ + ST_F ((void *)out, vd3, VL); OUT += VL; \ + +#define LOOP_DUAL_WIDEN_BINARY_BODY_X8(NT, WT, LD_NF, OUT_F, ST_F, OUT, \ + START, VL) \ + NT vs0 = LD_NF ((void *)START, VL); START += VL; \ + NT vs1 = LD_NF ((void *)START, VL); START += VL; \ + NT vs2 = LD_NF ((void *)START, VL); START += VL; \ + NT vs3 = LD_NF ((void *)START, VL); START += VL; \ + NT vs4 = LD_NF ((void *)START, VL); START += VL; \ + NT vs5 = LD_NF ((void *)START, VL); START += VL; \ + NT vs6 = LD_NF ((void *)START, VL); START += VL; \ + NT vs7 = LD_NF ((void *)START, VL); START += VL; \ + NT vt0 = LD_NF ((void *)START, VL); START += VL; \ + NT vt1 = LD_NF ((void *)START, VL); START += VL; \ + NT vt2 = LD_NF ((void *)START, VL); START += VL; \ + NT vt3 = LD_NF ((void *)START, VL); START += VL; \ + NT vt4 = LD_NF ((void *)START, VL); START += VL; \ + NT vt5 = LD_NF ((void *)START, VL); START += VL; \ + NT vt6 = LD_NF ((void *)START, VL); START += VL; \ + NT vt7 = LD_NF ((void *)START, VL); START += VL; \ + \ + asm volatile("nop" ::: "memory"); \ + \ + WT vd0 = OUT_F (vs0, vt0, VL); \ + WT vd1 = OUT_F (vs1, vt1, VL); \ + WT vd2 = OUT_F (vs2, vt2, VL); \ + WT vd3 = OUT_F (vs3, vt3, VL); \ + WT vd4 = OUT_F (vs4, vt4, VL); \ + WT vd5 = OUT_F (vs5, vt5, VL); \ + WT vd6 = OUT_F (vs6, vt6, VL); \ + WT vd7 = OUT_F (vs7, vt7, VL); \ + \ + asm volatile("nop" ::: "memory"); \ + \ + ST_F ((void *)out, vd0, VL); OUT += VL; \ + ST_F ((void *)out, vd1, VL); OUT += VL; \ + ST_F ((void *)out, vd2, VL); OUT += VL; \ + ST_F ((void *)out, vd3, VL); OUT += VL; \ + ST_F ((void *)out, vd4, VL); OUT += VL; \ + ST_F ((void *)out, vd5, VL); OUT += VL; \ + ST_F ((void *)out, vd6, VL); OUT += VL; \ + ST_F ((void *)out, vd7, VL); OUT += VL; \ + +#define LOOP_DUAL_WIDEN_BINARY_BODY_X16(NT, WT, LD_NF, OUT_F, ST_F, OUT, \ + START, VL) \ + NT vs0 = LD_NF ((void *)START, VL); START += VL; \ + NT vs1 = LD_NF ((void *)START, VL); START += VL; \ + NT vs2 = LD_NF ((void *)START, VL); START += VL; \ + NT vs3 = LD_NF ((void *)START, VL); START += VL; \ + NT vs4 = LD_NF ((void *)START, VL); START += VL; \ + NT vs5 = LD_NF ((void *)START, VL); START += VL; \ + NT vs6 = LD_NF ((void *)START, VL); START += VL; \ + NT vs7 = LD_NF ((void *)START, VL); START += VL; \ + NT vs8 = LD_NF ((void *)START, VL); START += VL; \ + NT vs9 = LD_NF ((void *)START, VL); START += VL; \ + NT vs10 = LD_NF ((void *)START, VL); START += VL; \ + NT vs11 = LD_NF ((void *)START, VL); START += VL; \ + NT vs12 = LD_NF ((void *)START, VL); START += VL; \ + NT vs13 = LD_NF ((void *)START, VL); START += VL; \ + NT vs14 = LD_NF ((void *)START, VL); START += VL; \ + NT vs15 = LD_NF ((void *)START, VL); START += VL; \ + NT vt0 = LD_NF ((void *)START, VL); START += VL; \ + NT vt1 = LD_NF ((void *)START, VL); START += VL; \ + NT vt2 = LD_NF ((void *)START, VL); START += VL; \ + NT vt3 = LD_NF ((void *)START, VL); START += VL; \ + NT vt4 = LD_NF ((void *)START, VL); START += VL; \ + NT vt5 = LD_NF ((void *)START, VL); START += VL; \ + NT vt6 = LD_NF ((void *)START, VL); START += VL; \ + NT vt7 = LD_NF ((void *)START, VL); START += VL; \ + NT vt8 = LD_NF ((void *)START, VL); START += VL; \ + NT vt9 = LD_NF ((void *)START, VL); START += VL; \ + NT vt10 = LD_NF ((void *)START, VL); START += VL; \ + NT vt11 = LD_NF ((void *)START, VL); START += VL; \ + NT vt12 = LD_NF ((void *)START, VL); START += VL; \ + NT vt13 = LD_NF ((void *)START, VL); START += VL; \ + NT vt14 = LD_NF ((void *)START, VL); START += VL; \ + NT vt15 = LD_NF ((void *)START, VL); START += VL; \ + \ + asm volatile("nop" ::: "memory"); \ + \ + WT vd0 = OUT_F (vs0, vt0, VL); \ + WT vd1 = OUT_F (vs1, vt1, VL); \ + WT vd2 = OUT_F (vs2, vt2, VL); \ + WT vd3 = OUT_F (vs3, vt3, VL); \ + WT vd4 = OUT_F (vs4, vt4, VL); \ + WT vd5 = OUT_F (vs5, vt5, VL); \ + WT vd6 = OUT_F (vs6, vt6, VL); \ + WT vd7 = OUT_F (vs7, vt7, VL); \ + WT vd8 = OUT_F (vs8, vt8, VL); \ + WT vd9 = OUT_F (vs9, vt9, VL); \ + WT vd10 = OUT_F (vs10, vt10, VL); \ + WT vd11 = OUT_F (vs11, vt11, VL); \ + WT vd12 = OUT_F (vs12, vt12, VL); \ + WT vd13 = OUT_F (vs13, vt13, VL); \ + WT vd14 = OUT_F (vs14, vt14, VL); \ + WT vd15 = OUT_F (vs15, vt15, VL); \ + \ + asm volatile("nop" ::: "memory"); \ + \ + ST_F ((void *)out, vd0, VL); OUT += VL; \ + ST_F ((void *)out, vd1, VL); OUT += VL; \ + ST_F ((void *)out, vd2, VL); OUT += VL; \ + ST_F ((void *)out, vd3, VL); OUT += VL; \ + ST_F ((void *)out, vd4, VL); OUT += VL; \ + ST_F ((void *)out, vd5, VL); OUT += VL; \ + ST_F ((void *)out, vd6, VL); OUT += VL; \ + ST_F ((void *)out, vd7, VL); OUT += VL; \ + ST_F ((void *)out, vd8, VL); OUT += VL; \ + ST_F ((void *)out, vd9, VL); OUT += VL; \ + ST_F ((void *)out, vd10, VL); OUT += VL; \ + ST_F ((void *)out, vd11, VL); OUT += VL; \ + ST_F ((void *)out, vd12, VL); OUT += VL; \ + ST_F ((void *)out, vd13, VL); OUT += VL; \ + ST_F ((void *)out, vd14, VL); OUT += VL; \ + ST_F ((void *)out, vd15, VL); OUT += VL; \ + #define DEF_GROUP_OVERLAP_UNARY_0(VL_F, NT, WT, LD_F, OUT_F, ST_F, NAME, \ LOOP_BODY) \ void test_group_overlap_##NAME##_##NT##_unary_0(uint8_t *data, \ @@ -282,4 +421,19 @@ } \ } +#define DEF_GROUP_OVERLAP_BINARY_1(VL_F, NT, WT, LD_NF, OUT_F, ST_F, NAME, \ + LOOP_BODY) \ + void test_group_overlap_##NAME##_##NT##_binary_1(uint8_t *data, \ + uint8_t *out, \ + size_t limit) \ + { \ + uint8_t *start = data; \ + uint8_t *end = data + limit; \ + size_t vl = VL_F (); \ + \ + while (start < end) { \ + LOOP_BODY (NT, WT, LD_NF, OUT_F, ST_F, out, start, vl); \ + } \ + } + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m1.c new file mode 100644 index 000000000000..aeedef57f308 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m1, + vint16m1_t, + vint32m2_t, + __riscv_vle16_v_i16m1, + __riscv_vwadd_vv_i32m2, + __riscv_vse32_v_i32m2, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m2.c new file mode 100644 index 000000000000..13878d778fd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m2, + vint16m2_t, + vint32m4_t, + __riscv_vle16_v_i16m2, + __riscv_vwadd_vv_i32m4, + __riscv_vse32_v_i32m4, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m4.c new file mode 100644 index 000000000000..22094ed2bc22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m4, + vint16m4_t, + vint32m8_t, + __riscv_vle16_v_i16m4, + __riscv_vwadd_vv_i32m8, + __riscv_vse32_v_i32m8, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf2.c new file mode 100644 index 000000000000..d61e103a63d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m1, + vint16mf2_t, + vint32m1_t, + __riscv_vle16_v_i16mf2, + __riscv_vwadd_vv_i32m1, + __riscv_vse32_v_i32m1, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf4.c new file mode 100644 index 000000000000..0afd594c19e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i16-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e16m1, + vint16mf4_t, + vint32mf2_t, + __riscv_vle16_v_i16mf4, + __riscv_vwadd_vv_i32mf2, + __riscv_vse32_v_i32mf2, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m1.c new file mode 100644 index 000000000000..fba485e89ca1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m1, + vint32m1_t, + vint64m2_t, + __riscv_vle32_v_i32m1, + __riscv_vwadd_vv_i64m2, + __riscv_vse64_v_i64m2, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m2.c new file mode 100644 index 000000000000..67a0953d412b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m2, + vint32m2_t, + vint64m4_t, + __riscv_vle32_v_i32m2, + __riscv_vwadd_vv_i64m4, + __riscv_vse64_v_i64m4, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m4.c new file mode 100644 index 000000000000..91eae13157b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m4, + vint32m4_t, + vint64m8_t, + __riscv_vle32_v_i32m4, + __riscv_vwadd_vv_i64m8, + __riscv_vse64_v_i64m8, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-mf2.c new file mode 100644 index 000000000000..25d1f5e46d9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i32-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e32m1, + vint32mf2_t, + vint64m1_t, + __riscv_vle32_v_i32mf2, + __riscv_vwadd_vv_i64m1, + __riscv_vse64_v_i64m1, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m1.c new file mode 100644 index 000000000000..cba1ed5eee35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e8m1, + vint8m1_t, + vint16m2_t, + __riscv_vle8_v_i8m1, + __riscv_vwadd_vv_i16m2, + __riscv_vse16_v_i16m2, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m2.c new file mode 100644 index 000000000000..c28d4861b22b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e8m2, + vint8m2_t, + vint16m4_t, + __riscv_vle8_v_i8m2, + __riscv_vwadd_vv_i16m4, + __riscv_vse16_v_i16m4, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m4.c new file mode 100644 index 000000000000..550b4f61ed1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e8m4, + vint8m4_t, + vint16m8_t, + __riscv_vle8_v_i8m4, + __riscv_vwadd_vv_i16m8, + __riscv_vse16_v_i16m8, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwadd\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf2.c new file mode 100644 index 000000000000..b9b604775659 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e8m1, + vint8mf2_t, + vint16m1_t, + __riscv_vle8_v_i8mf2, + __riscv_vwadd_vv_i16m1, + __riscv_vse16_v_i16m1, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf4.c new file mode 100644 index 000000000000..ae5ed27fbb57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e8m1, + vint8mf4_t, + vint16mf2_t, + __riscv_vle8_v_i8mf4, + __riscv_vwadd_vv_i16mf2, + __riscv_vse16_v_i16mf2, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf8.c new file mode 100644 index 000000000000..0c63738a6f9f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwadd_vv-i8-mf8.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_1( + __riscv_vsetvlmax_e8m1, + vint8mf8_t, + vint16mf4_t, + __riscv_vle8_v_i8mf8, + __riscv_vwadd_vv_i16mf4, + __riscv_vse16_v_i16mf4, + vwadd_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwadd\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */