[gcc r17-2973] Add ISA support for AVX10_V2_AUX and FP32 to FP8 single-source RTNE converts.
Venkataramanan Kumar via Gcc-cvs <[email protected]> Wed, 5 Aug 2026 09:46:40 +0000 (GMT)
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://gcc.gnu.org/g:9ab915926a4112475f1374498b1c7f6b9e39bb62 commit r17-2973-g9ab915926a4112475f1374498b1c7f6b9e39bb62 Author: Dipesh Sharma <[email protected]> Date: Sun Jul 19 14:49:15 2026 +0530 Add ISA support for AVX10_V2_AUX and FP32 to FP8 single-source RTNE converts. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add AVX10V2AUX. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10V2AUX_SET): New. (OPTION_MASK_ISA2_AVX10_1_UNSET): Disable AVX10_1. (OPTION_MASK_ISA2_AVX10V2AUX_UNSET): New. (ix86_handle_option): Handle AVX10V2AUX. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10V2AUX. * common/config/i386/i386-isas.h: Handle avx10v2aux. * config.gcc: Include avx10v2auxintrin.h. * config/i386/cpuid.h (bit_AVX10V2AUX): New. * config/i386/i386-builtin-types.def: Add new function type. * config/i386/i386-builtin.def (BDESC): New AVX10V2AUX builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle avx10v2aux. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle avx10v2aux function types. * config/i386/i386-isa.def (AVX10V2AUX): New DEF_PTA * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle avx10v2aux. * config/i386/i386.opt: Add avx10v2aux. * config/i386/i386.opt.urls: Regenerated. * config/i386/immintrin.h: Include avx10v2auxintrin.h. * config/i386/sse.md (vcvt<convertps2fp8>v4sf): New. (*vcvt<convertps2fp8>v4sf): Ditto. (vcvt<convertps2fp8>v8sf): Ditto. (*vcvt<convertps2fp8>v8sf): Ditto. (vcvt<convertps2fp8>v4sf_mask): Ditto. (*vcvt<convertps2fp8>v4sf_mask): Ditto. (vcvt<convertps2fp8>v8sf_mask): Ditto. (*vcvt<convertps2fp8>v8sf_mask): Ditto. (vcvt<convertps2fp8>v16sf<mask_name>): Ditto. * doc/extend.texi: Add avx10v2aux documentation. * doc/invoke.texi: Ditto. * doc/sourcebuild.texi: Ditto. * config/i386/avx10v2auxintrin.h: New file. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Check for avx10v2aux. * gcc.target/i386/avx10v2aux-convert-1a.c: New test. Co-authored-by: Venkataramanan Kumar <[email protected]> Co-authored-by: Haochen Jiang <[email protected]> Diff: --- gcc/common/config/i386/cpuinfo.h | 7 + gcc/common/config/i386/i386-common.cc | 22 +- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 2 + gcc/config.gcc | 3 +- gcc/config/i386/avx10v2auxintrin.h | 409 +++++++++++++++++++++ gcc/config/i386/cpuid.h | 4 + gcc/config/i386/i386-builtin-types.def | 5 + gcc/config/i386/i386-builtin.def | 14 + gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-expand.cc | 3 + gcc/config/i386/i386-isa.def | 1 + gcc/config/i386/i386-options.cc | 4 +- gcc/config/i386/i386.opt | 5 + gcc/config/i386/i386.opt.urls | 3 + gcc/config/i386/immintrin.h | 2 + gcc/config/i386/sse.md | 146 ++++++++ gcc/doc/extend.texi | 5 + gcc/doc/invoke.texi | 8 +- gcc/doc/sourcebuild.texi | 3 + .../gcc.target/i386/avx10v2aux-convert-1a.c | 111 ++++++ gcc/testsuite/lib/target-supports.exp | 11 + 22 files changed, 766 insertions(+), 5 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 0fe7eb795b08..f4fd3dbfed04 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -1124,6 +1124,7 @@ get_available_features (struct __processor_model *cpu_model, if (avx10_set && max_cpuid_level >= 0x24) { __cpuid_count (0x24, 0, eax, ebx, ecx, edx); + unsigned int max_subleaf_level = eax; version = ebx & 0xff; switch (version) { @@ -1137,6 +1138,12 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVX10_1); break; } + if (max_subleaf_level>=1) + { + __cpuid_count (0x24, 1, eax, ebx, ecx, edx); + if (ecx & bit_AVX10V2AUX) + set_feature (FEATURE_AVX10V2AUX); + } } /* Check cpuid level of extended features. */ diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 7c743f8b3486..931e9d8a16d4 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -138,7 +138,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AMX_MOVRS_SET \ (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_MOVRS) #define OPTION_MASK_ISA2_AVX512BMM_SET OPTION_MASK_ISA2_AVX512BMM - +#define OPTION_MASK_ISA2_AVX10V2AUX_SET \ + (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10V2AUX) /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET @@ -323,13 +324,15 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR #define OPTION_MASK_ISA2_AVX10_1_UNSET \ - (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET) + (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \ + | OPTION_MASK_ISA2_AVX10V2AUX_UNSET) #define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2 #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512 #define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8 #define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS #define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS #define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM +#define OPTION_MASK_ISA2_AVX10V2AUX_UNSET OPTION_MASK_ISA2_AVX10V2AUX /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -1414,6 +1417,21 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavx10v2aux: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10V2AUX_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10V2AUX_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_UNSET; + } + return true; + case OPT_mamx_avx512: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index a38534c53df7..5b9bf5db68b3 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -283,6 +283,7 @@ enum processor_features FEATURE_MOVRS, FEATURE_AMX_MOVRS, FEATURE_AVX512BMM, + FEATURE_AVX10V2AUX, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index f816d471252d..d280418c2617 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -191,4 +191,6 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("movrs", FEATURE_MOVRS, P_NONE, "-mmovrs") ISA_NAMES_TABLE_ENTRY("amx-movrs", FEATURE_AMX_MOVRS, P_NONE, "-mamx-movrs") ISA_NAMES_TABLE_ENTRY("avx512bmm", FEATURE_AVX512BMM, P_NONE, "-mavx512bmm") + ISA_NAMES_TABLE_ENTRY("avx10v2aux", FEATURE_AVX10V2AUX, P_NONE, + "-mavx10v2aux") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index 0477bf22c8a0..6968d666b89c 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -479,7 +479,8 @@ i[34567]86-*-* | x86_64-*-*) avx10_2bf16intrin.h avx10_2satcvtintrin.h avx10_2minmaxintrin.h avx10_2copyintrin.h amxavx512intrin.h amxfp8intrin.h movrsintrin.h - amxmovrsintrin.h avx512bmmintrin.h avx512bmmvlintrin.h" + amxmovrsintrin.h avx512bmmintrin.h avx512bmmvlintrin.h + avx10v2auxintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/avx10v2auxintrin.h b/gcc/config/i386/avx10v2auxintrin.h new file mode 100644 index 000000000000..23b008ce1d8f --- /dev/null +++ b/gcc/config/i386/avx10v2auxintrin.h @@ -0,0 +1,409 @@ +/* Copyright (C) 2026 Free Software Foundation, Inc. + This file is part of GCC. + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined _IMMINTRIN_H_INCLUDED +#error "Never use <avx10v2auxintrin.h> directly; include <immintrin.h> instead." + +#endif + +#ifndef _AVX10V2AUXINTRIN_H_INCLUDED +#define _AVX10V2AUXINTRIN_H_INCLUDED + +#if !defined(__AVX10V2AUX__) +#pragma GCC push_options +#pragma GCC target("avx10v2aux") +#define __DISABLE_AVX10V2AUX__ +#endif /* __AVX10V2AUX__ */ + +// VCVTPS2BF8 - 128-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvtps_bf8 (__m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8128_mask ((__v4sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvtps_bf8 (__m128i __W, __mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8128_mask ((__v4sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_cvtps_bf8 (__mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8128_mask ((__v4sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2BF8 - 256-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtps_bf8 (__m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8256_mask ((__v8sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtps_bf8 (__m128i __W, __mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8256_mask ((__v8sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtps_bf8 (__mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8256_mask ((__v8sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2BF8 - 512-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_cvtps_bf8 (__m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8512_mask ((__v16sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvtps_bf8 (__m128i __W, __mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8512_mask ((__v16sf) __A, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_cvtps_bf8 (__mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8512_mask ((__v16sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + +// VCVTPS2BF8S - 128-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvts_ps_bf8 (__m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s128_mask ((__v4sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvts_ps_bf8 (__m128i __W, __mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s128_mask ((__v4sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_cvts_ps_bf8 (__mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s128_mask ((__v4sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2BF8S - 256-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvts_ps_bf8 (__m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s256_mask ((__v8sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvts_ps_bf8 (__m128i __W, __mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s256_mask ((__v8sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvts_ps_bf8 (__mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s256_mask ((__v8sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2BF8S - 512-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_cvts_ps_bf8 (__m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s512_mask ((__v16sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvts_ps_bf8 (__m128i __W, __mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s512_mask ((__v16sf) __A, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_cvts_ps_bf8 (__mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2bf8s512_mask ((__v16sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + +// VCVTPS2HF8 - 128-bit +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvtps_hf8 (__m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8128_mask ((__v4sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvtps_hf8 (__m128i __W, __mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8128_mask ((__v4sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_cvtps_hf8 (__mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8128_mask ((__v4sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2HF8 - 256-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtps_hf8 (__m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8256_mask ((__v8sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtps_hf8 (__m128i __W, __mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8256_mask ((__v8sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtps_hf8 (__mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8256_mask ((__v8sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2HF8 - 512-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_cvtps_hf8 (__m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8512_mask ((__v16sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvtps_hf8 (__m128i __W, __mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8512_mask ((__v16sf) __A, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_cvtps_hf8 (__mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8512_mask ((__v16sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + +// VCVTPS2HF8S - 128-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvts_ps_hf8 (__m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s128_mask ((__v4sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvts_ps_hf8 (__m128i __W, __mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s128_mask ((__v4sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_cvts_ps_hf8 (__mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s128_mask ((__v4sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2HF8S - 256-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvts_ps_hf8 (__m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s256_mask ((__v8sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvts_ps_hf8 (__m128i __W, __mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s256_mask ((__v8sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvts_ps_hf8 (__mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s256_mask ((__v8sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTPS2HF8S - 512-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_cvts_ps_hf8 (__m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s512_mask ((__v16sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvts_ps_hf8 (__m128i __W, __mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s512_mask ((__v16sf) __A, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_cvts_ps_hf8 (__mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtps2hf8s512_mask ((__v16sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + +#ifdef __DISABLE_AVX10V2AUX__ +#undef __DISABLE_AVX10V2AUX__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX10V2AUX__ */ + +#endif /* _AVX10V2AUXINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index a1024e0a9408..c56ad7cce80e 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -170,6 +170,10 @@ /* Sub leaf (%eax == 0x21) */ #define bit_AVX512BMM ( 1<<23 ) +/* AVX10 sub leaf (%eax == 0x24, %ecx == 1) */ +/* %ecx */ +#define bit_AVX10V2AUX (1 << 3) + /* AMX sub leaf (%eax == 0x1e, %ecx == 1) */ /* %eax */ #define bit_AMX_FP8 (1 << 4) diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index 64bde021d117..34e0cf7f8d3b 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1474,6 +1474,11 @@ DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, UQI) DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, UQI) DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, UQI) +# AVX10V2AUX builtins +DEF_FUNCTION_TYPE (V16QI, V4SF, V16QI, UQI) +DEF_FUNCTION_TYPE (V16QI, V8SF, V16QI, UQI) +DEF_FUNCTION_TYPE (V16QI, V16SF, V16QI, UHI) + # SM4 builtins DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 30e728ab15d1..ef872de98bf3 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -3369,6 +3369,20 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv2df_mask, "__builti BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv8hf_mask, "__builtin_ia32_minmaxph128_mask", IX86_BUILTIN_MINMAXPH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_INT_V8HF_UQI) BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv4sf_mask, "__builtin_ia32_minmaxps128_mask", IX86_BUILTIN_MINMAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI) +/* AVX10V2AUX. */ +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2bf8v4sf_mask, "__builtin_ia32_vcvtps2bf8128_mask", IX86_BUILTIN_VCVTPS2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2bf8v8sf_mask, "__builtin_ia32_vcvtps2bf8256_mask", IX86_BUILTIN_VCVTPS2BF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2bf8v16sf_mask, "__builtin_ia32_vcvtps2bf8512_mask", IX86_BUILTIN_VCVTPS2BF8512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2bf8sv4sf_mask, "__builtin_ia32_vcvtps2bf8s128_mask", IX86_BUILTIN_VCVTPS2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2bf8sv8sf_mask, "__builtin_ia32_vcvtps2bf8s256_mask", IX86_BUILTIN_VCVTPS2BF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2bf8sv16sf_mask, "__builtin_ia32_vcvtps2bf8s512_mask", IX86_BUILTIN_VCVTPS2BF8S512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8v4sf_mask, "__builtin_ia32_vcvtps2hf8128_mask", IX86_BUILTIN_VCVTPS2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8v8sf_mask, "__builtin_ia32_vcvtps2hf8256_mask", IX86_BUILTIN_VCVTPS2HF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8v16sf_mask, "__builtin_ia32_vcvtps2hf8512_mask", IX86_BUILTIN_VCVTPS2HF8512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8sv4sf_mask, "__builtin_ia32_vcvtps2hf8s128_mask", IX86_BUILTIN_VCVTPS2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8sv8sf_mask, "__builtin_ia32_vcvtps2hf8s256_mask", IX86_BUILTIN_VCVTPS2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8sv16sf_mask, "__builtin_ia32_vcvtps2hf8s512_mask", IX86_BUILTIN_VCVTPS2HF8S512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI) + /* Builtins with rounding support. */ BDESC_END (ARGS, ROUND_ARGS) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index e1145725b62b..4c56ff6dad9c 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -790,6 +790,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__AMX_MOVRS__"); if (isa_flag2 & OPTION_MASK_ISA2_AVX512BMM) def_or_undef (parse_in, "__AVX512BMM__"); + if (isa_flag2 & OPTION_MASK_ISA2_AVX10V2AUX) + def_or_undef (parse_in, "__AVX10V2AUX__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 6ddc402e9ad4..5adbfe7b4c93 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -13058,6 +13058,9 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V8DI_FTYPE_V8SF_V8DI_UQI: case V8DI_FTYPE_V8DF_V8DI_UQI: case V8SI_FTYPE_V8DF_V8SI_UQI: + case V16QI_FTYPE_V4SF_V16QI_UQI: + case V16QI_FTYPE_V8SF_V16QI_UQI: + case V16QI_FTYPE_V16SF_V16QI_UHI: nargs = 3; break; case V32QI_FTYPE_V32QI_V32QI_INT: diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 72f448e80a47..e50cb6768fa7 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -125,3 +125,4 @@ DEF_PTA(AMX_FP8) DEF_PTA(MOVRS) DEF_PTA(AMX_MOVRS) DEF_PTA(AVX512BMM) +DEF_PTA(AVX10V2AUX) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index a9d31714f13f..afbd96b79c33 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -274,7 +274,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mamx-fp8", OPTION_MASK_ISA2_AMX_FP8 }, { "-mmovrs", OPTION_MASK_ISA2_MOVRS }, { "-mamx-movrs", OPTION_MASK_ISA2_AMX_MOVRS }, - { "-mavx512bmm", OPTION_MASK_ISA2_AVX512BMM } + { "-mavx512bmm", OPTION_MASK_ISA2_AVX512BMM }, + { "-mavx10v2aux", OPTION_MASK_ISA2_AVX10V2AUX } }; static struct ix86_target_opts isa_opts[] = { @@ -1139,6 +1140,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("movrs", OPT_mmovrs), IX86_ATTR_ISA ("amx-movrs", OPT_mamx_movrs), IX86_ATTR_ISA ("avx512bmm", OPT_mavx512bmm), + IX86_ATTR_ISA ("avx10v2aux", OPT_mavx10v2aux), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 158090c2bde7..2cdc71a2324e 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1385,3 +1385,8 @@ Support AMX-MOVRS built-in functions and code generation. mavx512bmm Target Mask(ISA2_AVX512BMM) Var(ix86_isa_flags2) Save Support AVX512BMM built-in functions and code generation. + +mavx10v2aux +Target Mask(ISA2_AVX10V2AUX) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +AVX10.1 and AVX10V2AUX built-in functions and code generation. diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index 5ae63d6b520f..d0c58ca35267 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -632,3 +632,6 @@ UrlSuffix(gcc/x86-Options.html#index-mamx-movrs) mavx512bmm UrlSuffix(gcc/x86-Options.html#index-mavx512bmm) +mavx10v2aux +UrlSuffix(gcc/x86-Options.html#index-mavx10v2aux) + diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index b978395dee06..2c55e1e02a37 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -146,6 +146,8 @@ #include <avx10_2convertintrin.h> +#include <avx10v2auxintrin.h> + #include <avx10_2bf16intrin.h> #include <avx10_2satcvtintrin.h> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7d71f8ba5462..2b5998cff0a6 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -258,6 +258,12 @@ ;; For MOVRS support UNSPEC_VMOVRS + + ;; For AVX10V2AUX support + UNSPEC_VCVTPS2BF8 + UNSPEC_VCVTPS2BF8S + UNSPEC_VCVTPS2HF8 + UNSPEC_VCVTPS2HF8S ]) (define_c_enum "unspecv" [ @@ -34217,3 +34223,143 @@ "vbitrevb\t{%1, %0|%0, %1}" [(set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) + +;; AVX10V2AUX instructions +;; FP32 to FP8 single-source converts (VCVTPS2BF8, VCVTPS2BF8S, +;; VCVTPS2HF8, VCVTPS2HF8S) + +(define_int_iterator UNSPEC_CONVERTPS2FP8 + [UNSPEC_VCVTPS2BF8 UNSPEC_VCVTPS2BF8S + UNSPEC_VCVTPS2HF8 UNSPEC_VCVTPS2HF8S]) + +(define_int_attr convertps2fp8 + [(UNSPEC_VCVTPS2BF8 "ps2bf8") + (UNSPEC_VCVTPS2BF8S "ps2bf8s") + (UNSPEC_VCVTPS2HF8 "ps2hf8") + (UNSPEC_VCVTPS2HF8S "ps2hf8s")]) + +(define_expand "vcvt<convertps2fp8>v4sf" + [(set (match_operand:V16QI 0 "register_operand") + (vec_concat:V16QI + (unspec:V4QI + [(match_operand:V4SF 1 "nonimmediate_operand")] + UNSPEC_CONVERTPS2FP8) + (match_dup 2)))] + "TARGET_AVX10V2AUX" + "operands[2] = CONST0_RTX (V12QImode);") + +(define_insn "*vcvt<convertps2fp8>v4sf" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (unspec:V4QI + [(match_operand:V4SF 1 "nonimmediate_operand" "vm")] + UNSPEC_CONVERTPS2FP8) + (match_operand:V12QI 2 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vcvt<convertps2fp8>{x}\t{%1, %0|%0, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "V4SF")]) + +(define_expand "vcvt<convertps2fp8>v8sf" + [(set (match_operand:V16QI 0 "register_operand") + (vec_concat:V16QI + (unspec:V8QI + [(match_operand:V8SF 1 "nonimmediate_operand")] + UNSPEC_CONVERTPS2FP8) + (match_dup 2)))] + "TARGET_AVX10V2AUX" + "operands[2] = CONST0_RTX (V8QImode);") + +(define_insn "*vcvt<convertps2fp8>v8sf" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (unspec:V8QI + [(match_operand:V8SF 1 "nonimmediate_operand" "vm")] + UNSPEC_CONVERTPS2FP8) + (match_operand:V8QI 2 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vcvt<convertps2fp8>{y}\t{%1, %0|%0, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "V8SF")]) + +(define_expand "vcvt<convertps2fp8>v4sf_mask" + [(set (match_operand:V16QI 0 "register_operand") + (vec_concat:V16QI + (vec_merge:V4QI + (unspec:V4QI + [(match_operand:V4SF 1 "nonimmediate_operand")] + UNSPEC_CONVERTPS2FP8) + (vec_select:V4QI + (match_operand:V16QI 2 "nonimm_or_0_operand") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)])) + (match_operand:QI 3 "register_operand")) + (match_dup 4)))] + "TARGET_AVX10V2AUX" + "operands[4] = CONST0_RTX (V12QImode);") + +(define_insn "*vcvt<convertps2fp8>v4sf_mask" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (vec_merge:V4QI + (unspec:V4QI + [(match_operand:V4SF 1 "nonimmediate_operand" "vm")] + UNSPEC_CONVERTPS2FP8) + (vec_select:V4QI + (match_operand:V16QI 2 "nonimm_or_0_operand" "0C") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)])) + (match_operand:QI 3 "register_operand" "Yk")) + (match_operand:V12QI 4 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vcvt<convertps2fp8>{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "V4SF")]) + +(define_expand "vcvt<convertps2fp8>v8sf_mask" + [(set (match_operand:V16QI 0 "register_operand") + (vec_concat:V16QI + (vec_merge:V8QI + (unspec:V8QI + [(match_operand:V8SF 1 "nonimmediate_operand")] + UNSPEC_CONVERTPS2FP8) + (vec_select:V8QI + (match_operand:V16QI 2 "nonimm_or_0_operand") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])) + (match_operand:QI 3 "register_operand")) + (match_dup 4)))] + "TARGET_AVX10V2AUX" + "operands[4] = CONST0_RTX (V8QImode);") + +(define_insn "*vcvt<convertps2fp8>v8sf_mask" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (vec_merge:V8QI + (unspec:V8QI + [(match_operand:V8SF 1 "nonimmediate_operand" "vm")] + UNSPEC_CONVERTPS2FP8) + (vec_select:V8QI + (match_operand:V16QI 2 "nonimm_or_0_operand" "0C") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])) + (match_operand:QI 3 "register_operand" "Yk")) + (match_operand:V8QI 4 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vcvt<convertps2fp8>{y}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "V8SF")]) + +(define_insn "vcvt<convertps2fp8>v16sf<mask_name>" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI + [(match_operand:V16SF 1 "nonimmediate_operand" "vm")] + UNSPEC_CONVERTPS2FP8))] + "TARGET_AVX10V2AUX" + "vcvt<convertps2fp8>{z}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "V16SF")]) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 16ce7908d91b..9a3f158792d7 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -9509,6 +9509,11 @@ Enable/disable the generation of the MOVRS instructions. @itemx no-amx-movrs Enable/disable the generation of the AMX-MOVRS instructions. +@atindex @code{target("avx10v2aux")}, x86 +@item avx10v2aux +@itemx no-avx10v2aux +Enable/disable the generation of the AVX10V2AUX instructions. + @atindex @code{target("cld")}, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d3de8e88c3b1..7c65c9242716 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1553,7 +1553,7 @@ See RS/6000 and PowerPC Options. -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf -musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mmovrs -mamx-movrs --mavx512bmm +-mavx512bmm -mavx10v2aux -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -36241,6 +36241,12 @@ Support MOVRS built-in functions and code generation. @opindex mno-amx-movrs @item -mamx-movrs Support AMX-MOVRS built-in functions and code generation. + +@opindex mavx10v2aux +@opindex mno-avx10v2aux +@item -mavx10v2aux +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +AVX10.1 and AVX10V2AUX built-in functions and code generation. @end table These additional options are available for the x86 processor family. diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 2c41583ced51..aad51550eba4 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2688,6 +2688,9 @@ Target supports compiling @code{avx} instructions. @item avx_runtime Target supports the execution of @code{avx} instructions. +@item avx10v2aux +Target supports the execution of @code{avx10v2aux} instructions. + @item avx10.1 Target supports the execution of @code{avx10.1} instructions. diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1a.c b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1a.c new file mode 100644 index 000000000000..2a89cc19e3d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1a.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2bf8sz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8x\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8y\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8z\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2hf8sz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128 a1; +volatile __m256 a2; +volatile __m512 a3; +volatile __m128i x128i; +volatile __mmask8 m8; +volatile __mmask16 m16; + +void extern +avx10v2aux_vcvtps2bf8_test (void) +{ + x128i = _mm_cvtps_bf8 (a1); + x128i = _mm_mask_cvtps_bf8 (x128i, m8, a1); + x128i = _mm_maskz_cvtps_bf8 (m8, a1); + + x128i = _mm256_cvtps_bf8 (a2); + x128i = _mm256_mask_cvtps_bf8 (x128i, m8, a2); + x128i = _mm256_maskz_cvtps_bf8 (m8, a2); + + x128i = _mm512_cvtps_bf8 (a3); + x128i = _mm512_mask_cvtps_bf8 (x128i, m16, a3); + x128i = _mm512_maskz_cvtps_bf8 (m16, a3); +} + +void extern +avx10v2aux_vcvtps2bf8s_test (void) +{ + x128i = _mm_cvts_ps_bf8 (a1); + x128i = _mm_mask_cvts_ps_bf8 (x128i, m8, a1); + x128i = _mm_maskz_cvts_ps_bf8 (m8, a1); + + x128i = _mm256_cvts_ps_bf8 (a2); + x128i = _mm256_mask_cvts_ps_bf8 (x128i, m8, a2); + x128i = _mm256_maskz_cvts_ps_bf8 (m8, a2); + + x128i = _mm512_cvts_ps_bf8 (a3); + x128i = _mm512_mask_cvts_ps_bf8 (x128i, m16, a3); + x128i = _mm512_maskz_cvts_ps_bf8 (m16, a3); +} + +void extern +avx10v2aux_vcvtps2hf8_test (void) +{ + x128i = _mm_cvtps_hf8 (a1); + x128i = _mm_mask_cvtps_hf8 (x128i, m8, a1); + x128i = _mm_maskz_cvtps_hf8 (m8, a1); + + x128i = _mm256_cvtps_hf8 (a2); + x128i = _mm256_mask_cvtps_hf8 (x128i, m8, a2); + x128i = _mm256_maskz_cvtps_hf8 (m8, a2); + + x128i = _mm512_cvtps_hf8 (a3); + x128i = _mm512_mask_cvtps_hf8 (x128i, m16, a3); + x128i = _mm512_maskz_cvtps_hf8 (m16, a3); +} + +void extern +avx10v2aux_vcvtps2hf8s_test (void) +{ + x128i = _mm_cvts_ps_hf8 (a1); + x128i = _mm_mask_cvts_ps_hf8 (x128i, m8, a1); + x128i = _mm_maskz_cvts_ps_hf8 (m8, a1); + + x128i = _mm256_cvts_ps_hf8 (a2); + x128i = _mm256_mask_cvts_ps_hf8 (x128i, m8, a2); + x128i = _mm256_maskz_cvts_ps_hf8 (m8, a2); + + x128i = _mm512_cvts_ps_hf8 (a3); + x128i = _mm512_mask_cvts_ps_hf8 (x128i, m16, a3); + x128i = _mm512_maskz_cvts_ps_hf8 (m16, a3); +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 42cbb5ce3df0..dafbebe84ca7 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -11680,6 +11680,17 @@ proc check_effective_target_avx10_2 { } { } "" ] } +# Return 1 if avx10v2aux instructions can be compiled. +proc check_effective_target_avx10v2aux { } { + return [check_no_compiler_messages avx10v2aux object { + void + foo () + { + __asm__ volatile ("vcvtps2bf8\t{%%xmm1, %%xmm0|%%xmm0, %%xmm1}"); + } + } "-mavx10v2aux" ] +} + # Return 1 if amx-avx512 instructions can be compiled. proc check_effective_target_amx_avx512 { } { return [check_no_compiler_messages amx_avx512 object {