[gcc r17-2974] Add FP32 to FP8 Single-Source RTO converts.
Venkataramanan Kumar via Gcc-cvs <[email protected]> Wed, 5 Aug 2026 09:49:14 +0000 (GMT)
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https://gcc.gnu.org/g:50e5bb1da91a1e2025a1d040eddc95d2dbaa9148 commit r17-2974-g50e5bb1da91a1e2025a1d040eddc95d2dbaa9148 Author: Dipesh Sharma <[email protected]> Date: Sun Jul 19 15:07:05 2026 +0530 Add FP32 to FP8 Single-Source RTO converts. gcc/ChangeLog: * config/i386/avx10v2auxintrin.h:(_mm_cvtrops_hf8): New intrins. (_mm_mask_cvtrops_hf8): Ditto. (_mm_maskz_cvtrops_hf8): Ditto. (_mm256_cvtrops_hf8): Ditto. (_mm256_mask_cvtrops_hf8): Ditto. (_mm256_maskz_cvtrops_hf8): Ditto. (_mm512_cvtrops_hf8): Ditto. (_mm512_mask_cvtrops_hf8): Ditto. (_mm512_maskz_cvtrops_hf8): Ditto. (_mm_cvts_rops_hf8): Ditto. (_mm_mask_cvts_rops_hf8): Ditto. (_mm_maskz_cvts_rops_hf8): Ditto. (_mm256_cvts_rops_hf8): Ditto. (_mm256_mask_cvts_rops_hf8): Ditto. (_mm256_maskz_cvts_rops_hf8): Ditto. (_mm512_cvts_rops_hf8): Ditto. (_mm512_mask_cvts_rops_hf8): Ditto. (_mm512_maskz_cvts_rops_hf8): Ditto. * config/i386/i386-builtin.def (BDESC): New avx10v2aux builtins. * config/i386/sse.md: Add RTO UNSPEC. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10v2aux-convert-1b.c: New test. Co-authored-by: Venkataramanan Kumar <[email protected]> Co-authored-by: Haochen Jiang <[email protected]> Diff: --- gcc/config/i386/avx10v2auxintrin.h | 186 +++++++++++++++++++++ gcc/config/i386/i386-builtin.def | 6 + gcc/config/i386/sse.md | 11 +- .../gcc.target/i386/avx10v2aux-convert-1b.c | 61 +++++++ 4 files changed, 261 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/avx10v2auxintrin.h b/gcc/config/i386/avx10v2auxintrin.h index 23b008ce1d8f..3183052b3a3b 100644 --- a/gcc/config/i386/avx10v2auxintrin.h +++ b/gcc/config/i386/avx10v2auxintrin.h @@ -401,6 +401,192 @@ _mm512_maskz_cvts_ps_hf8 (__mmask16 __U, __m512 __A) (__mmask16) __U); } +// VCVTROPS2HF8 - 128-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvtrops_hf8 (__m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8128_mask ((__v4sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvtrops_hf8 (__m128i __W, __mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8128_mask ((__v4sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_cvtrops_hf8 (__mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8128_mask ((__v4sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTROPS2HF8 - 256-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtrops_hf8 (__m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8256_mask ((__v8sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtrops_hf8 (__m128i __W, __mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8256_mask ((__v8sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtrops_hf8 (__mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8256_mask ((__v8sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTROPS2HF8 - 512-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_cvtrops_hf8 (__m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8512_mask ((__v16sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvtrops_hf8 (__m128i __W, __mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8512_mask ((__v16sf) __A, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_cvtrops_hf8 (__mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8512_mask ((__v16sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + +// VCVTROPS2HF8S - 128-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvts_rops_hf8 (__m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s128_mask ((__v4sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvts_rops_hf8 (__m128i __W, __mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s128_mask ((__v4sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_cvts_rops_hf8 (__mmask8 __U, __m128 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s128_mask ((__v4sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTROPS2HF8S - 256-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvts_rops_hf8 (__m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s256_mask ((__v8sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvts_rops_hf8 (__m128i __W, __mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s256_mask ((__v8sf) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvts_rops_hf8 (__mmask8 __U, __m256 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s256_mask ((__v8sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +// VCVTROPS2HF8S - 512-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_cvts_rops_hf8 (__m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s512_mask ((__v16sf) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvts_rops_hf8 (__m128i __W, __mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s512_mask ((__v16sf) __A, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_cvts_rops_hf8 (__mmask16 __U, __m512 __A) +{ + return (__m128i) __builtin_ia32_vcvtrops2hf8s512_mask ((__v16sf) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + #ifdef __DISABLE_AVX10V2AUX__ #undef __DISABLE_AVX10V2AUX__ #pragma GCC pop_options diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index ef872de98bf3..e20a21aec1c0 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -3382,6 +3382,12 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8v16sf_mask, "__builtin BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8sv4sf_mask, "__builtin_ia32_vcvtps2hf8s128_mask", IX86_BUILTIN_VCVTPS2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI) BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8sv8sf_mask, "__builtin_ia32_vcvtps2hf8s256_mask", IX86_BUILTIN_VCVTPS2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI) BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtps2hf8sv16sf_mask, "__builtin_ia32_vcvtps2hf8s512_mask", IX86_BUILTIN_VCVTPS2HF8S512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8v4sf_mask, "__builtin_ia32_vcvtrops2hf8128_mask", IX86_BUILTIN_VCVTROPS2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8v8sf_mask, "__builtin_ia32_vcvtrops2hf8256_mask", IX86_BUILTIN_VCVTROPS2HF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8v16sf_mask, "__builtin_ia32_vcvtrops2hf8512_mask", IX86_BUILTIN_VCVTROPS2HF8512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8sv4sf_mask, "__builtin_ia32_vcvtrops2hf8s128_mask", IX86_BUILTIN_VCVTROPS2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8sv8sf_mask, "__builtin_ia32_vcvtrops2hf8s256_mask", IX86_BUILTIN_VCVTROPS2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8sv16sf_mask, "__builtin_ia32_vcvtrops2hf8s512_mask", IX86_BUILTIN_VCVTROPS2HF8S512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI) /* Builtins with rounding support. */ BDESC_END (ARGS, ROUND_ARGS) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2b5998cff0a6..e06d43f66026 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -264,6 +264,8 @@ UNSPEC_VCVTPS2BF8S UNSPEC_VCVTPS2HF8 UNSPEC_VCVTPS2HF8S + UNSPEC_VCVTROPS2HF8 + UNSPEC_VCVTROPS2HF8S ]) (define_c_enum "unspecv" [ @@ -34226,17 +34228,20 @@ ;; AVX10V2AUX instructions ;; FP32 to FP8 single-source converts (VCVTPS2BF8, VCVTPS2BF8S, -;; VCVTPS2HF8, VCVTPS2HF8S) +;; VCVTPS2HF8, VCVTPS2HF8S, VCVTROPS2HF8, VCVTROPS2HF8S) (define_int_iterator UNSPEC_CONVERTPS2FP8 [UNSPEC_VCVTPS2BF8 UNSPEC_VCVTPS2BF8S - UNSPEC_VCVTPS2HF8 UNSPEC_VCVTPS2HF8S]) + UNSPEC_VCVTPS2HF8 UNSPEC_VCVTPS2HF8S + UNSPEC_VCVTROPS2HF8 UNSPEC_VCVTROPS2HF8S]) (define_int_attr convertps2fp8 [(UNSPEC_VCVTPS2BF8 "ps2bf8") (UNSPEC_VCVTPS2BF8S "ps2bf8s") (UNSPEC_VCVTPS2HF8 "ps2hf8") - (UNSPEC_VCVTPS2HF8S "ps2hf8s")]) + (UNSPEC_VCVTPS2HF8S "ps2hf8s") + (UNSPEC_VCVTROPS2HF8 "rops2hf8") + (UNSPEC_VCVTROPS2HF8S "rops2hf8s")]) (define_expand "vcvt<convertps2fp8>v4sf" [(set (match_operand:V16QI 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1b.c b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1b.c new file mode 100644 index 000000000000..7d2a03fb6daf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1b.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8x\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8y\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8z\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8z\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8z\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sx\[ \\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sy\[ \\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sz\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sz\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtrops2hf8sz\[ \\t\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128 a1; +volatile __m256 a2; +volatile __m512 a3; +volatile __m128i x128i; +volatile __mmask8 m8; +volatile __mmask16 m16; + +void extern +avx10v2aux_vcvtrops2hf8_test (void) +{ + x128i = _mm_cvtrops_hf8 (a1); + x128i = _mm_mask_cvtrops_hf8 (x128i, m8, a1); + x128i = _mm_maskz_cvtrops_hf8 (m8, a1); + + x128i = _mm256_cvtrops_hf8 (a2); + x128i = _mm256_mask_cvtrops_hf8 (x128i, m8, a2); + x128i = _mm256_maskz_cvtrops_hf8 (m8, a2); + + x128i = _mm512_cvtrops_hf8 (a3); + x128i = _mm512_mask_cvtrops_hf8 (x128i, m16, a3); + x128i = _mm512_maskz_cvtrops_hf8 (m16, a3); +} + +void extern +avx10v2aux_vcvtrops2hf8s_test (void) +{ + x128i = _mm_cvts_rops_hf8 (a1); + x128i = _mm_mask_cvts_rops_hf8 (x128i, m8, a1); + x128i = _mm_maskz_cvts_rops_hf8 (m8, a1); + + x128i = _mm256_cvts_rops_hf8 (a2); + x128i = _mm256_mask_cvts_rops_hf8 (x128i, m8, a2); + x128i = _mm256_maskz_cvts_rops_hf8 (m8, a2); + + x128i = _mm512_cvts_rops_hf8 (a3); + x128i = _mm512_mask_cvts_rops_hf8 (x128i, m16, a3); + x128i = _mm512_maskz_cvts_rops_hf8 (m16, a3); +}