[gcc r17-3511] aarch64: Fix comments for register constraints

https://gcc.gnu.org/g:0c84051bd679d0060b0e8832463672b914b8f1ab

commit r17-3511-g0c84051bd679d0060b0e8832463672b914b8f1ab
Author: Karl Meakin <[email protected]>
Date:   Tue Nov 25 18:24:04 2025 +0000

    aarch64: Fix comments for register constraints
    
    The comments for the "w", "x" and "y" register constraints in
    gcc/config/aarch64/constraints.md were misleading. They apply to SVE
    registers as well as Advanced SIMD and FP registers.
    
    gcc/ChangeLog:
    
            * config/aarch64/constraints.md: Fix comments.

Diff:
---
 gcc/config/aarch64/constraints.md | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 847739e32709..99fa24c2a30f 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -40,20 +40,20 @@
    veneer.")
 
 (define_register_constraint "w" "FP_REGS"
-  "Floating point and SIMD vector registers.")
+  "SVE/AdvSIMD/FP registers, V0 - V31.")
 
 (define_register_constraint "x" "FP_LO_REGS"
-  "Floating point and SIMD vector registers V0 - V15.")
+  "SVE/AdvSIMD/FP registers, V0 - V15.")
 
 (define_register_constraint "y" "FP_LO8_REGS"
-  "Floating point and SIMD vector registers V0 - V7.")
+  "SVE/AdvSIMD/FP  registers, V0 - V7.")
 
 (define_register_constraint "Uw2" "FP_REGS"
-  "Even floating point and SIMD vector registers."
+  "Even SVE/AdvSIMD/FP registers, V0, V2, ..., V30."
   "regno % 2 == 0")
 
 (define_register_constraint "Uw4" "FP_REGS"
-  "4-tuple-aligned floating point and SIMD vector registers."
+  "4-tuple-aligned SVE/AdvSIMD/FP registers, V0, V4, ..., V28."
   "regno % 4 == 0")
 
 (define_register_constraint "Uwd" "FP_REGS"