[gcc r17-3513] aarch64: Add `SME_MOP4` instrinsics and corresponding insns
Karl Meakin via Gcc-cvs <[email protected]>
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https://gcc.gnu.org/g:7cb08c33f1d35c1e2976f319916ee750ef609f31 commit r17-3513-g7cb08c33f1d35c1e2976f319916ee750ef609f31 Author: Karl Meakin <[email protected]> Date: Thu Dec 4 17:38:45 2025 +0000 aarch64: Add `SME_MOP4` instrinsics and corresponding insns Add support for the intrinsics added by the `+sme-mop4` extension: * svmop4a[_1x1]_za32[_f32] * svmop4a[_1x1]_za32[_f16_f16] * svmop4a[_1x1]_za32[_bf16_bf16] * svmop4a[_1x1]_za32[_s16_s16] * svmop4a[_1x1]_za32[_u16_u16] * svmop4a[_1x1]_za32[_s8_s8] * svmop4a[_1x1]_za32[_u8_u8] * svmop4a[_1x1]_za32[_s8_u8] * svmop4a[_1x1]_za32[_u8_s8] * svmop4a[_1x1]_za16[_f16_f16] (only if __ARM_FEATURE_SME_F16F16 != 0) * svmop4a[_1x1]_za16[_bf16_bf16] (only if __ARM_FEATURE_SME_B16B16 != 0) * svmop4a[_1x1]_za64[_f64_f64] (only if __ARM_FEATURE_SME_F64F64 != 0) * svmop4a[_1x1]_za64[_s16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) * svmop4a[_1x1]_za64[_u16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) * svmop4a[_1x1]_za64[_s16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) * svmop4a[_1x1]_za64[_u16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) * svmop4a[_1x1]_za16[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F16 != 0) * svmop4a[_1x1]_za32[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F32 != 0) plus all `_1x2`, `_2x1`, `_2x2` and `svmop4s` variants. Also add new SVE mode suffixes (1x1, 1x2, 2x1 and 2x2) and register constraints (z, Ux2, Uz2) as necessary. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_hard_regno_nregs, aarch64_class_max_nregs): Handle `FP_HI_REGS`. * config/aarch64/aarch64-acle-builtins.h (mop4_base, mop4_b16b16, mop4_f8f16, mop4_f8f32, mop4_f64f64, mop4_i16i64): New type arrays. * config/aarch64/aarch64.h (reg_class::FP_HI_REGS): New enum member. * config/aarch64/aarch64-sve-builtins-shapes.cc (struct mop4_def): New function shape. * config/aarch64/aarch64-sve-builtins-shapes.h: New function shape. * config/aarch64/aarch64-sve-builtins-sme.def (DEF_SME_FUNCTION): Unconditionally define in terms of `DEF_SME_FUNCTION_GS`. (DEF_SME_ZA_FUNCTION_GS): Unconditionally define in terms of `DEF_SME_ZA_FUNCTION_GS_FPM`. (DEF_SME_ZA_FUNCTION): Unconditionally define in terms of `DEF_SME_ZA_FUNCTION_GS`. (svmop4a, svmop4s): New function groups. (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION_GS_FPM): New macros. * config/aarch64/aarch64-sve-builtins.def (1x1, 1x2, 2x1, 2x2): New SVE function modes. * config/aarch64/constraints.md (z, Ux2, Uxz): New register constraints. * config/aarch64/aarch64-sme.md (@aarch64_mop4_): New insns. * config/aarch64/aarch64-sve-builtins-functions.h (class sme_mop4): New function base. * config/aarch64/aarch64-sve-builtins-sme.cc (svmop4a_za, svmop4s_za): New functions. * config/aarch64/aarch64-sve-builtins-sme.h (svmop4a_za, svmop4s_za): New function bases. * config/aarch64/iterators.md: New mode iterators. (UNSPEC_SME_FMOP4A, UNSPEC_SME_FMOP4S, UNSPEC_SME_UMOP4A, UNSPEC_SME_UMOP4S, UNSPEC_SME_SMOP4A, UNSPEC_SME_SMOP4S, UNSPEC_SME_SUMOP4A, UNSPEC_SME_SUMOP4S, UNSPEC_SME_USMOP4A, UNSPEC_SME_USMOP4S): New unspecs. (SME_FP_MOP4, SME_FP8_MOP4, SME_INT_MOP4): New int iterators. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sme/acle-asm/test_sme_acle.h (TEST_UNIFORM_ZA, TEST_DUAL_ZA): Add new `fpm_t fpm0` arguments. * gcc.target/aarch64/sve/acle/general-c/mop4_b16b16.c: New test. * gcc.target/aarch64/sve/acle/general-c/mop4_base.c: New test. * gcc.target/aarch64/sve/acle/general-c/mop4_f16f16.c: New test. * gcc.target/aarch64/sve/acle/general-c/mop4_f64f64.c: New test. * gcc.target/aarch64/sve/acle/general-c/mop4_f8f16.c: New test. * gcc.target/aarch64/sve/acle/general-c/mop4_f8f32.c: New test. * gcc.target/aarch64/sve/acle/general-c/mop4_i16i64.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c: New test. Diff: --- gcc/config/aarch64/aarch64-acle-builtins.h | 57 +++++++++ gcc/config/aarch64/aarch64-sme.md | 133 +++++++++++++++++++++ .../aarch64/aarch64-sve-builtins-functions.h | 52 ++++++++ gcc/config/aarch64/aarch64-sve-builtins-shapes.cc | 45 +++++++ gcc/config/aarch64/aarch64-sve-builtins-shapes.h | 1 + gcc/config/aarch64/aarch64-sve-builtins-sme.cc | 6 + gcc/config/aarch64/aarch64-sve-builtins-sme.def | 67 +++++++++++ gcc/config/aarch64/aarch64-sve-builtins-sme.h | 2 + gcc/config/aarch64/aarch64-sve-builtins.def | 4 + gcc/config/aarch64/aarch64.cc | 2 + gcc/config/aarch64/aarch64.h | 3 + gcc/config/aarch64/constraints.md | 11 ++ gcc/config/aarch64/iterators.md | 65 ++++++++++ .../aarch64/sme/acle-asm/test_sme_acle.h | 2 +- .../aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c | 87 ++++++++++++++ .../aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c | 87 ++++++++++++++ .../aarch64/sve/acle/general-c/mop4_b16b16.c | 79 ++++++++++++ .../aarch64/sve/acle/general-c/mop4_base.c | 106 ++++++++++++++++ .../aarch64/sve/acle/general-c/mop4_f16f16.c | 79 ++++++++++++ .../aarch64/sve/acle/general-c/mop4_f64f64.c | 79 ++++++++++++ .../aarch64/sve/acle/general-c/mop4_f8f16.c | 84 +++++++++++++ .../aarch64/sve/acle/general-c/mop4_f8f32.c | 84 +++++++++++++ .../aarch64/sve/acle/general-c/mop4_i16i64.c | 88 ++++++++++++++ 54 files changed, 3919 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64-acle-builtins.h b/gcc/config/aarch64/aarch64-acle-builtins.h index 8dd5e1387195..481a294c9382 100644 --- a/gcc/config/aarch64/aarch64-acle-builtins.h +++ b/gcc/config/aarch64/aarch64-acle-builtins.h @@ -1815,6 +1815,56 @@ function_expander::result_mode () const #define TYPES_mop_i16i64_unsigned(S, D, T) \ D (za64, u16) +// svmop4a[_1x1]_za32[_f32] +// svmop4a[_1x1]_za32[_f16_f16] +// svmop4a[_1x1]_za32[_bf16_bf16] +// svmop4a[_1x1]_za32[_s16_s16] +// svmop4a[_1x1]_za32[_u16_u16] +// svmop4a[_1x1]_za32[_s8_s8] +// svmop4a[_1x1]_za32[_u8_u8] +// svmop4a[_1x1]_za32[_s8_u8] +// svmop4a[_1x1]_za32[_u8_s8] +#define TYPES_mop4_base(S, D, T) \ + T (za32, f32, f32), \ + T (za32, f16, f16), \ + T (za32, bf16, bf16), \ + T (za32, s16, s16), \ + T (za32, u16, u16), \ + T (za32, s8, s8), \ + T (za32, u8, u8), \ + T (za32, s8, u8), \ + T (za32, u8, s8) + +// svmop4a[_1x1]_za16[_bf16_bf16] (only if __ARM_FEATURE_SME_B16B16 != 0) +#define TYPES_mop4_b16b16(S, D, T) \ + T (za16, bf16, bf16) + +// svmop4a[_1x1]_za16[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F16 != 0) +#define TYPES_mop4_f8f16(S, D, T) \ + T (za16, mf8, mf8) + +// svmop4a[_1x1]_za32[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F32 != 0) +#define TYPES_mop4_f8f32(S, D, T) \ + T (za32, mf8, mf8) + +// svmop4a[_1x1]_za16[_f16_f16] (only if __ARM_FEATURE_SME_F16F16 != 0) +#define TYPES_mop4_f16f16(S, D, T) \ + T (za16, f16, f16) + +// svmop4a[_1x1]_za64[_f64_f64] (only if __ARM_FEATURE_SME_F64F64 != 0) +#define TYPES_mop4_f64f64(S, D, T) \ + T (za64, f64, f64) + +// svmop4a[_1x1]_za64[_s16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_u16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_s16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_u16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) +#define TYPES_mop4_i16i64(S, D, T) \ + T (za64, s16, s16), \ + T (za64, u16, u16), \ + T (za64, s16, u16), \ + T (za64, u16, s16) + /* _za. */ #define TYPES_za(S, D, T) \ S (za) @@ -2107,6 +2157,13 @@ DEF_SVE_TYPES_ARRAY (mop_base_unsigned); DEF_SVE_TYPES_ARRAY (mop_i16i64); DEF_SVE_TYPES_ARRAY (mop_i16i64_signed); DEF_SVE_TYPES_ARRAY (mop_i16i64_unsigned); +DEF_SVE_TYPES_ARRAY (mop4_f16f16); +DEF_SVE_TYPES_ARRAY (mop4_b16b16); +DEF_SVE_TYPES_ARRAY (mop4_base); +DEF_SVE_TYPES_ARRAY (mop4_f64f64); +DEF_SVE_TYPES_ARRAY (mop4_i16i64); +DEF_SVE_TYPES_ARRAY (mop4_f8f16); +DEF_SVE_TYPES_ARRAY (mop4_f8f32); DEF_SVE_TYPES_ARRAY (za); DEF_SVE_TYPES_ARRAY (b_float); diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md index 7091f566ba8d..9685824d22ea 100644 --- a/gcc/config/aarch64/aarch64-sme.md +++ b/gcc/config/aarch64/aarch64-sme.md @@ -1814,6 +1814,55 @@ "<optab>\tza%0.s, %1/m, %2/m, %3.s, %4.s" ) +;; _za32_s16_s16 +;; _za32_u16_u16 +(define_insn "@aarch64_mop4_<optab><VNx4SI_ONLY:mode><SVE_FULL_HIx12:mode><SVE_FULL_HIx12_2:mode>" + [(set (reg:VNx4SI_ONLY ZA_REGNUM) + (unspec:VNx4SI_ONLY + [(reg:VNx4SI_ONLY ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_HIx12 1 "aligned_register_operand" "Ux2") + (match_operand:SVE_FULL_HIx12_2 2 "aligned_register_operand" "Uz2")] + SME_INT_MOP4))] + "TARGET_SME_MOP4" + "<optab>\tza%0.<VNx4SI_ONLY:Vetype>, %1<SVE_FULL_HIx12:z_suffix>, %2<SVE_FULL_HIx12_2:z_suffix>" +) + +;; _za32_s8_s8 +;; _za32_u8_u8 +;; _za32_s8_u8 +;; _za32_u8_s8 +(define_insn "@aarch64_mop4_<optab><VNx4SI_ONLY:mode><SVE_FULL_BIx12:mode><SVE_FULL_BIx12_2:mode>" + [(set (reg:VNx4SI_ONLY ZA_REGNUM) + (unspec:VNx4SI_ONLY + [(reg:VNx4SI_ONLY ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_BIx12 1 "aligned_register_operand" "Ux2") + (match_operand:SVE_FULL_BIx12_2 2 "aligned_register_operand" "Uz2")] + SME_INT_MOP4))] + "TARGET_SME_MOP4" + "<optab>\tza%0.<VNx4SI_ONLY:Vetype>, %1<SVE_FULL_BIx12:z_suffix>, %2<SVE_FULL_BIx12_2:z_suffix>" +) + +;; _za64_s16_s16 (only if __ARM_FEATURE_SME_I16I64 != 0) +;; _za64_u16_u16 (only if __ARM_FEATURE_SME_I16I64 != 0) +;; _za64_s16_u16 (only if __ARM_FEATURE_SME_I16I64 != 0) +;; _za64_u16_s16 (only if __ARM_FEATURE_SME_I16I64 != 0) +(define_insn "@aarch64_mop4_<optab><VNx2DI_ONLY:Vetype><SVE_FULL_HIx12:mode><SVE_FULL_HIx12_2:mode>" + [(set (reg:VNx2DI_ONLY ZA_REGNUM) + (unspec:VNx2DI_ONLY + [(reg:VNx2DI_ONLY ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_HIx12 1 "aligned_register_operand" "Ux2") + (match_operand:SVE_FULL_HIx12_2 2 "aligned_register_operand" "Uz2")] + SME_INT_MOP4))] + "TARGET_SME_MOP4 && TARGET_SME_I16I64" + "<optab>\tza%0.<VNx2DI_ONLY:Vetype>, %1<SVE_FULL_HIx12:z_suffix>, %2<SVE_FULL_HIx12_2:z_suffix>" +) + ;; ------------------------------------------------------------------------- ;; ---- [FP] Dot product ;; ------------------------------------------------------------------------- @@ -2689,6 +2738,16 @@ ;; - FMOPS ;; - FMOPA (SME_F8F16) ;; - FMOPA (SME_F8F32) +;; - BFMOP4A (SME_B16B16) +;; - BFMOP4S (SME_B16B16) +;; - UMOP4A (SME_MOP4) +;; - UMOP4S (SME_MOP4) +;; - SMOP4A (SME_MOP4) +;; - SMOP4S (SME_MOP4) +;; - SUMOP4A (SME_MOP4) +;; - USMOP4S (SME_MOP4) +;; - FMOP4A (SME_MOP4) +;; - FMOP4S (SME_MOP4) ;; ------------------------------------------------------------------------- (define_insn "@aarch64_sme_<optab><mode><mode>" @@ -2737,6 +2796,80 @@ "<optab>\tza%0.<SME_ZA_F8F16_32:Vetype>, %1/m, %2/m, %3.b, %4.b" ) +;; _za16_f16_f16 (only if __ARM_FEATURE_SME_F16F16 != 0) +;; _za32_f16_f16 +(define_insn "@aarch64_mop4_<optab><SME_MOP4_F16:mode><SVE_FULL_HF_NO_BFx12:mode><SVE_FULL_HF_NO_BFx12_2:mode>" + [(set (reg:SME_MOP4_F16 ZA_REGNUM) + (unspec:SME_MOP4_F16 + [(reg:SME_MOP4_F16 ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_HF_NO_BFx12 1 "aligned_register_operand" "Ux2") + (match_operand:SVE_FULL_HF_NO_BFx12_2 2 "aligned_register_operand" "Uz2")] + SME_FP_MOP4))] + "TARGET_SME_MOP4" + "<optab>\tza%0.<SME_MOP4_F16:Vetype>, %1<SVE_FULL_HF_NO_BFx12:z_suffix>, %2<SVE_FULL_HF_NO_BFx12_2:z_suffix>" +) + +;; _za16_bf16_bf16 (only if __ARM_FEATURE_SME_B16B16 != 0) +;; _za32_bf16_bf16 +(define_insn "@aarch64_mop4_<optab><SME_MOP4_BF16:mode><SVE_FULL_BFx12:mode><SVE_FULL_BFx12_2:mode>" + [(set (reg:SME_MOP4_BF16 ZA_REGNUM) + (unspec:SME_MOP4_BF16 + [(reg:SME_MOP4_BF16 ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_BFx12 1 "aligned_register_operand" "Ux2") + (match_operand:SVE_FULL_BFx12_2 2 "aligned_register_operand" "Uz2")] + SME_FP_MOP4))] + "TARGET_SME_MOP4" + "b<optab>\tza%0.<SME_MOP4_BF16:Vetype>, %1<SVE_FULL_BFx12:z_suffix>, %2<SVE_FULL_BFx12_2:z_suffix>" +) + +;; _za32_f32_f32 +(define_insn "@aarch64_mop4_<optab><VNx4SI_ONLY:mode><SVE_FULL_SFx12:mode><SVE_FULL_SFx12_2:mode>" + [(set (reg:VNx4SI_ONLY ZA_REGNUM) + (unspec:VNx4SI_ONLY + [(reg:VNx4SI_ONLY ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_SFx12 1 "aligned_register_operand" "Ux2") + (match_operand:SVE_FULL_SFx12_2 2 "aligned_register_operand" "Uz2")] + SME_FP_MOP4))] + "TARGET_SME_MOP4" + "<optab>\tza%0.<VNx4SI_ONLY:Vetype>, %1<SVE_FULL_SFx12:z_suffix>, %2<SVE_FULL_SFx12_2:z_suffix>" +) + +;; _za64_f64_f64 (only if __ARM_FEATURE_SME_F64F64 != 0) +(define_insn "@aarch64_mop4_<optab><VNx2DI_ONLY:mode><SVE_FULL_DFx12:mode><SVE_FULL_DFx12_2:mode>" + [(set (reg:VNx2DI_ONLY ZA_REGNUM) + (unspec:VNx2DI_ONLY + [(reg:VNx2DI_ONLY ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_DFx12 1 "register_operand" "Ux2") + (match_operand:SVE_FULL_DFx12_2 2 "register_operand" "Uz2")] + SME_FP_MOP4))] + "TARGET_SME_MOP4 && TARGET_SME_F64F64" + "<optab>\tza%0.<VNx2DI_ONLY:Vetype>, %1<SVE_FULL_DFx12:z_suffix>, %2<SVE_FULL_DFx12_2:z_suffix>" +) + +;; _za16_mf8_mf8_fpm (only if __ARM_FEATURE_SME_F8F16 != 0) +;; _za32_mf8_mf8_fpm (only if __ARM_FEATURE_SME_F8F32 != 0) +(define_insn "@aarch64_mop4_<optab><SME_ZA_MF8:mode><SVE_FULL_BIx12:mode><SVE_FULL_BIx12_2:mode>" + [(set (reg:SME_ZA_MF8 ZA_REGNUM) + (unspec:SME_ZA_MF8 + [(reg:SME_ZA_MF8 ZA_REGNUM) + (reg:DI SME_STATE_REGNUM) + (match_operand:DI 0 "const_int_operand") + (match_operand:SVE_FULL_BIx12 1 "register_operand" "Ux2") + (match_operand:SVE_FULL_BIx12_2 2 "register_operand" "Uz2") + (reg:DI FPM_REGNUM)] + SME_FP8_MOP4))] + "TARGET_SME_MOP4" + "<optab>\tza%0.<SME_ZA_MF8:Vetype>, %1<SVE_FULL_BIx12:z_suffix>, %2<SVE_FULL_BIx12_2:z_suffix>" +) + ;; ========================================================================= ;; == Table lookup ;; ========================================================================= diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h index ebbefaf739e5..9fe8e5dcccec 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h @@ -508,6 +508,58 @@ public: } }; +class sme_mop4 : public read_write_za<unspec_based_function_base> +{ +private: + unspec m_unspec_for_suint; + unspec m_unspec_for_usint; + +public: + using parent = read_write_za<unspec_based_function_base>; + + constexpr sme_mop4 (unspec unspec_for_sint, unspec unspec_for_uint, + unspec unspec_for_fp, unspec unspec_for_suint, + unspec unspec_for_usint) + : parent (unspec_for_sint, unspec_for_uint, + unspec_for_fp, unspec_for_fp, 1), + m_unspec_for_suint (unspec_for_suint), + m_unspec_for_usint (unspec_for_usint) + {} + + rtx expand (function_expander &e) const override + { + machine_mode za_mode = e.vector_mode (0); + machine_mode v1_mode = e.tuple_mode (1); + machine_mode v2_mode = e.tuple_mode (1); + + switch (e.mode_suffix_id) + { + case MODE_1x1: + break; + case MODE_1x2: + v2_mode = targetm.array_mode (v2_mode, 2).require (); + break; + case MODE_2x1: + v1_mode = targetm.array_mode (v1_mode, 2).require (); + break; + case MODE_2x2: + v1_mode = targetm.array_mode (v1_mode, 2).require (); + v2_mode = targetm.array_mode (v2_mode, 2).require (); + break; + default: + gcc_unreachable (); + } + + unspec unspec = (e.type_suffix (1).unsigned_p == e.type_suffix (2).unsigned_p) + ? unspec_for (e) + : (e.type_suffix (1).unsigned_p ? m_unspec_for_usint + : m_unspec_for_suint); + + insn_code icode = code_for_aarch64_mop4 (unspec, za_mode, v1_mode, v2_mode); + return e.use_exact_insn (icode); + } +}; + using sme_2mode_function = sme_2mode_function_t<code_for_aarch64_sme, code_for_aarch64_sme_single>; diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc index cf128bc94646..af12db249d8d 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc @@ -3464,6 +3464,51 @@ SHAPE (luti4_lane_zt); using luti4_zt_def = luti_zt_base<4>; SHAPE (luti4_zt); +struct mop4_def : public overloaded_base<1> +{ + void build (function_builder &b, + const function_group_info &group) const override + { + b.add_overloaded_functions (group, MODE_none); + build_all (b, "_,su64,v1,v2", group, MODE_1x1); + build_all (b, "_,su64,v1,u2", group, MODE_1x2); + build_all (b, "_,su64,u1,v2", group, MODE_2x1); + build_all (b, "_,su64,u1,u2", group, MODE_2x2); + } + + tree resolve (function_resolver &r) const override + { + mode_suffix_index mode = MODE_1x1; + sve_type type1; + sve_type type2; + + if (!r.check_num_arguments (3 + (r.fpm_mode == FPM_set)) + || !r.require_scalar_type (0, "uint64_t") + || !r.require_integer_immediate (0) + || !(type1 = r.infer_sve_type (1)) + || !(type2 = r.infer_sve_type (2))) + return error_mark_node; + + if (type1.num_vectors == 1 && type2.num_vectors == 1) + mode = MODE_1x1; + else if (type1.num_vectors == 1 && type2.num_vectors == 2) + mode = MODE_1x2; + else if (type1.num_vectors == 2 && type2.num_vectors == 1) + mode = MODE_2x1; + else if (type1.num_vectors == 2 && type2.num_vectors == 2) + mode = MODE_2x2; + + return r.resolve_to (mode, r.type_suffix_ids[0], type1.type, type2.type, + GROUP_none); + } + + bool check (function_checker &c) const override + { + return c.require_immediate_range (0, 0, c.num_za_tiles () - 1); + } +}; +SHAPE (mop4); + /* svbool_t svfoo(enum svpattern). */ struct pattern_pred_def : public nonoverloaded_base { diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.h b/gcc/config/aarch64/aarch64-sve-builtins-shapes.h index 0fca00b36d1d..c7c8b300c8ea 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.h @@ -173,6 +173,7 @@ namespace aarch64_acle extern const function_shape *const luti4_lane_zt; extern const function_shape *const luti4_zt; extern const function_shape *const mmla; + extern const function_shape *const mop4; extern const function_shape *const pattern_pred; extern const function_shape *const pmov_from_vector; extern const function_shape *const pmov_from_vector_lane; diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc index f2def0fb8374..0d36d16fb020 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc @@ -652,6 +652,12 @@ FUNCTION (svmls_za, sme_2mode_function, (UNSPEC_SME_SMLS, UNSPEC_SME_UMLS, FUNCTION (svmls_lane_za, sme_2mode_lane_function, (UNSPEC_SME_SMLS, UNSPEC_SME_UMLS, UNSPEC_SME_FMLS)) +FUNCTION (svmop4a_za, sme_mop4, + (UNSPEC_SME_SMOP4A, UNSPEC_SME_UMOP4A, UNSPEC_SME_FMOP4A, + UNSPEC_SME_SUMOP4A, UNSPEC_SME_USMOP4A)) +FUNCTION (svmop4s_za, sme_mop4, + (UNSPEC_SME_SMOP4S, UNSPEC_SME_UMOP4S, UNSPEC_SME_FMOP4S, + UNSPEC_SME_SUMOP4S, UNSPEC_SME_USMOP4S)) FUNCTION (svmopa_za, sme_2mode_function, (UNSPEC_SME_SMOPA, UNSPEC_SME_UMOPA, UNSPEC_SME_FMOPA, UNSPEC_SME_FMOPA)) FUNCTION (svmops_za, sme_2mode_function, (UNSPEC_SME_SMOPS, UNSPEC_SME_UMOPS, diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def index fa2de697e0bc..9aaca87e1f80 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def @@ -313,6 +313,73 @@ DEF_SME_ZA_FUNCTION_GS_FPM (svmla, binary_za_slice_opt_single, za_s_mf8, vg1x24, DEF_SME_ZA_FUNCTION_GS_FPM (svmopa, binary_za_m, za_s_mf8, none, za_m, set) #undef REQUIRED_EXTENSIONS +// All svmop4a functions also have `_1x2`, `2x1` and `2x2` variants, and all +// functions except `mf8_mf8` have `svmop4s` variants. + +// svmop4a[_1x1]_za32[_f32_f32] +// svmop4a[_1x1]_za32[_f16_f16] +// svmop4a[_1x1]_za32[_bf16_bf16] +// svmop4a[_1x1]_za32[_s16_s16] +// svmop4a[_1x1]_za32[_u16_u16] +// svmop4a[_1x1]_za32[_s8_s8] +// svmop4a[_1x1]_za32[_u8_u8] +// svmop4a[_1x1]_za32[_s8_u8] +// svmop4a[_1x1]_za32[_u8_s8] +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 \ + | AARCH64_FL_SME_MOP4) +DEF_SME_ZA_FUNCTION_GS (svmop4a, mop4, mop4_base, none, none) +DEF_SME_ZA_FUNCTION_GS (svmop4s, mop4, mop4_base, none, none) +#undef REQUIRED_EXTENSIONS + +// svmop4a[_1x1]_za16[_f16_f16] (only if __ARM_FEATURE_SME_F16F16 != 0) +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 \ + | AARCH64_FL_SME_MOP4 \ + | AARCH64_FL_SME_F16F16) +DEF_SME_ZA_FUNCTION_GS (svmop4a, mop4, mop4_f16f16, none, none) +DEF_SME_ZA_FUNCTION_GS (svmop4s, mop4, mop4_f16f16, none, none) +#undef REQUIRED_EXTENSIONS + +// svmop4a[_1x1]_za16[_bf16_bf16] (only if __ARM_FEATURE_SME_B16B16 != 0) +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 \ + | AARCH64_FL_SME_MOP4 \ + | AARCH64_FL_SME_B16B16) +DEF_SME_ZA_FUNCTION_GS (svmop4a, mop4, mop4_b16b16, none, none) +DEF_SME_ZA_FUNCTION_GS (svmop4s, mop4, mop4_b16b16, none, none) +#undef REQUIRED_EXTENSIONS + +// svmop4a[_1x1]_za64[_f64_f64] (only if __ARM_FEATURE_SME_F64F64 != 0) +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 \ + | AARCH64_FL_SME_MOP4 \ + | AARCH64_FL_SME_F64F64) +DEF_SME_ZA_FUNCTION_GS (svmop4a, mop4, mop4_f64f64, none, none) +DEF_SME_ZA_FUNCTION_GS (svmop4s, mop4, mop4_f64f64, none, none) +#undef REQUIRED_EXTENSIONS + +// svmop4a[_1x1]_za64[_s16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_u16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_s16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_u16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 \ + | AARCH64_FL_SME_MOP4 \ + | AARCH64_FL_SME_I16I64) +DEF_SME_ZA_FUNCTION_GS (svmop4a, mop4, mop4_i16i64, none, none) +DEF_SME_ZA_FUNCTION_GS (svmop4s, mop4, mop4_i16i64, none, none) +#undef REQUIRED_EXTENSIONS + +// svmop4a[_1x1]_za16[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F16 != 0) +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 \ + | AARCH64_FL_SME_MOP4 \ + | AARCH64_FL_SME_F8F16) +DEF_SME_ZA_FUNCTION_GS_FPM (svmop4a, mop4, mop4_f8f16, none, none, set) +#undef REQUIRED_EXTENSIONS + +// svmop4a[_1x1]_za32[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F32 != 0) +#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2 \ + | AARCH64_FL_SME_MOP4 \ + | AARCH64_FL_SME_F8F32) +DEF_SME_ZA_FUNCTION_GS_FPM (svmop4a, mop4, mop4_f8f32, none, none, set) +#undef REQUIRED_EXTENSIONS + #undef DEF_SME_ZA_FUNCTION #undef DEF_SME_ZA_FUNCTION_GS #undef DEF_SME_ZA_FUNCTION_GS_FPM diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.h b/gcc/config/aarch64/aarch64-sve-builtins-sme.h index cc264ea84869..d9166b8d0bc4 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.h @@ -51,6 +51,8 @@ namespace aarch64_acle extern const function_base *const svmla_lane_za; extern const function_base *const svmls_za; extern const function_base *const svmls_lane_za; + extern const function_base *const svmop4a_za; + extern const function_base *const svmop4s_za; extern const function_base *const svmopa_za; extern const function_base *const svmops_za; extern const function_base *const svread_za; diff --git a/gcc/config/aarch64/aarch64-sve-builtins.def b/gcc/config/aarch64/aarch64-sve-builtins.def index 0036a2e46dda..23508e90dc0f 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.def +++ b/gcc/config/aarch64/aarch64-sve-builtins.def @@ -119,6 +119,10 @@ DEF_SVE_MODE (u64base_u64offset, svuint64_t, svuint64_t, bytes) DEF_SVE_MODE (u64index, none, svuint64_t, elements) DEF_SVE_MODE (u64offset, none, svuint64_t, bytes) DEF_SVE_MODE (vnum, none, none, vectors) +DEF_SVE_MODE (1x1, none, none, none) +DEF_SVE_MODE (1x2, none, none, none) +DEF_SVE_MODE (2x1, none, none, none) +DEF_SVE_MODE (2x2, none, none, none) DEF_SVE_TYPE (svbool_t, 10, __SVBool_t, boolean_type_node) DEF_SVE_TYPE (svcount_t, 11, __SVCount_t, boolean_type_node) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index f36864a10da3..4671a47d3950 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -2456,6 +2456,7 @@ aarch64_hard_regno_nregs (unsigned regno, machine_mode mode) case FP_REGS: case FP_LO_REGS: case FP_LO8_REGS: + case FP_HI_REGS: { unsigned int vec_flags = aarch64_classify_vector_mode (mode); if (vec_flags & VEC_SVE_DATA) @@ -14293,6 +14294,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode) case FP_REGS: case FP_LO_REGS: case FP_LO8_REGS: + case FP_HI_REGS: vec_flags = aarch64_classify_vector_mode (mode); if ((vec_flags & VEC_SVE_DATA) && constant_multiple_p (GET_MODE_SIZE (mode), diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 6e16c1ca5854..fdedb0439112 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -931,6 +931,7 @@ enum reg_class POINTER_REGS, FP_LO8_REGS, FP_LO_REGS, + FP_HI_REGS, FP_REGS, POINTER_AND_FP_REGS, PR_LO_REGS, @@ -958,6 +959,7 @@ enum reg_class "POINTER_REGS", \ "FP_LO8_REGS", \ "FP_LO_REGS", \ + "FP_HI_REGS", \ "FP_REGS", \ "POINTER_AND_FP_REGS", \ "PR_LO_REGS", \ @@ -982,6 +984,7 @@ enum reg_class { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ + { 0x00000000, 0xffff0000, 0x00000000 }, /* FP_HI_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 99fa24c2a30f..4094212bbc84 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -48,6 +48,17 @@ (define_register_constraint "y" "FP_LO8_REGS" "SVE/AdvSIMD/FP registers, V0 - V7.") +(define_register_constraint "z" "FP_HI_REGS" + "SVE/AdvSIMD/FP registers, V16 - V31.") + +(define_register_constraint "Ux2" "FP_LO_REGS" + "Even SVE/AdvSIMD/FP registers, V0, V2, ..., V14." + "regno % 2 == 0") + +(define_register_constraint "Uz2" "FP_HI_REGS" + "Even SVE/AdvSIMD/FP registers, V16, V18, ..., V30." + "regno % 2 == 0") + (define_register_constraint "Uw2" "FP_REGS" "Even SVE/AdvSIMD/FP registers, V0, V2, ..., V30." "regno % 2 == 0") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 1bc20d6151c9..798c0d055ae2 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -560,6 +560,14 @@ (VNx4SF "TARGET_SVE2p1_OR_SME2") (VNx2DF "TARGET_SVE2p1_OR_SME2")]) +;; {u8, s8, mf8}{x1,x2} +(define_mode_iterator SVE_FULL_BIx12 [VNx16QI VNx32QI]) +(define_mode_iterator SVE_FULL_BIx12_2 [SVE_FULL_BIx12]) + +;; {u16, s16}{x1,x2} +(define_mode_iterator SVE_FULL_HIx12 [VNx8HI VNx16HI]) +(define_mode_iterator SVE_FULL_HIx12_2 [SVE_FULL_HIx12]) + ;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements. (define_mode_iterator SVE_FULL_BHI [VNx16QI VNx8HI]) @@ -576,6 +584,10 @@ ;; Pairs of the above. (define_mode_iterator SVE_FULL_HFx2 [VNx16BF VNx16HF]) +;; {f16}{x1,x2} +(define_mode_iterator SVE_FULL_HF_NO_BFx12 [VNx8HF VNx16HF]) +(define_mode_iterator SVE_FULL_HF_NO_BFx12_2 [SVE_FULL_HF_NO_BFx12]) + ;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements. (define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI VNx8BF VNx8HF VNx4SF VNx2DF]) @@ -596,6 +608,18 @@ ;; elements. (define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF]) +;; {bf16}{x1,x2} +(define_mode_iterator SVE_FULL_BFx12 [VNx8BF VNx16BF]) +(define_mode_iterator SVE_FULL_BFx12_2 [SVE_FULL_BFx12]) + +;; {f32}{x1,x2} +(define_mode_iterator SVE_FULL_SFx12 [VNx4SF VNx8SF]) +(define_mode_iterator SVE_FULL_SFx12_2 [SVE_FULL_SFx12]) + +;; {f64, f64x2} +(define_mode_iterator SVE_FULL_DFx12 [VNx2DF VNx4DF]) +(define_mode_iterator SVE_FULL_DFx12_2 [SVE_FULL_DFx12]) + ;; Like SVE_FULL_HSF, but selectively enables those modes that are valid ;; for the variant of the SVE2 FP8 FDOT instruction associated with that ;; mode. @@ -812,6 +836,9 @@ (define_mode_iterator SME_ZA_I [VNx16QI VNx8HI VNx4SI VNx2DI VNx1TI]) (define_mode_iterator SME_ZA_SDI [VNx4SI (VNx2DI "TARGET_SME_I16I64")]) +(define_mode_iterator SME_ZA_MF8 [(VNx8HI "TARGET_STREAMING_SME_F8F16") + (VNx4SI "TARGET_STREAMING_SME_F8F32")]) + (define_mode_iterator SME_ZA_BIx24 [VNx32QI VNx64QI]) (define_mode_iterator SME_ZA_BHIx124 [VNx16QI VNx32QI VNx64QI @@ -858,6 +885,15 @@ (VNx2DF "TARGET_SME_F64F64") (VNx8HF "TARGET_STREAMING_SME_F16F16") (VNx8BF "TARGET_STREAMING_SME_B16B16")]) +(define_mode_iterator SME_MOP4_F16 [ + (VNx8HI "TARGET_STREAMING_SME_F16F16") + VNx4SI +]) + +(define_mode_iterator SME_MOP4_BF16 [ + (VNx8HI "TARGET_STREAMING_SME_B16B16") + VNx4SI +]) ;; ------------------------------------------------------------------ ;; Unspec enumerations for Advance SIMD. These could well go into @@ -1364,6 +1400,8 @@ UNSPEC_SME_FMLA UNSPEC_SME_FMLAL UNSPEC_SME_FMLS + UNSPEC_SME_FMOP4A + UNSPEC_SME_FMOP4S UNSPEC_SME_FMOPA UNSPEC_SME_FMOPS UNSPEC_SME_FSUB @@ -1379,6 +1417,8 @@ UNSPEC_SME_SVDOT UNSPEC_SME_SMLA UNSPEC_SME_SMLS + UNSPEC_SME_SMOP4A + UNSPEC_SME_SMOP4S UNSPEC_SME_SMOPA UNSPEC_SME_SMOPS UNSPEC_SME_ST1_HOR @@ -1387,16 +1427,22 @@ UNSPEC_SME_SUB_WRITE UNSPEC_SME_SUDOT UNSPEC_SME_SUVDOT + UNSPEC_SME_SUMOP4A + UNSPEC_SME_SUMOP4S UNSPEC_SME_SUMOPA UNSPEC_SME_SUMOPS UNSPEC_SME_UDOT UNSPEC_SME_UVDOT UNSPEC_SME_UMLA UNSPEC_SME_UMLS + UNSPEC_SME_UMOP4A + UNSPEC_SME_UMOP4S UNSPEC_SME_UMOPA UNSPEC_SME_UMOPS UNSPEC_SME_USDOT UNSPEC_SME_USVDOT + UNSPEC_SME_USMOP4A + UNSPEC_SME_USMOP4S UNSPEC_SME_USMOPA UNSPEC_SME_USMOPS UNSPEC_SME_WRITE @@ -2989,6 +3035,8 @@ (define_mode_attr z_suffix [(VNx16QI ".b") (VNx32QI "") (VNx64QI "") (VNx8BF ".h") (VNx16BF "") (VNx32BF "") (VNx8HF ".h") (VNx16HF "") (VNx32HF "") + (VNx4SF ".s") (VNx8SF "") (VNx16SF "") + (VNx2DF ".d") (VNx4DF "") (VNx8DF "") (VNx8HI ".h") (VNx16HI "") (VNx32HI "")]) ;; The number of bytes controlled by a predicate @@ -4316,6 +4364,13 @@ (define_int_iterator SME_FP_MOP [UNSPEC_SME_FMOPA UNSPEC_SME_FMOPS]) +(define_int_iterator SME_FP_MOP4 [UNSPEC_SME_FMOP4A UNSPEC_SME_FMOP4S]) +(define_int_iterator SME_FP8_MOP4 [UNSPEC_SME_FMOP4A]) +(define_int_iterator SME_INT_MOP4 [UNSPEC_SME_UMOP4A UNSPEC_SME_UMOP4S + UNSPEC_SME_SMOP4A UNSPEC_SME_SMOP4S + UNSPEC_SME_SUMOP4A UNSPEC_SME_SUMOP4S + UNSPEC_SME_USMOP4A UNSPEC_SME_USMOP4S]) + (define_int_iterator SME2_BMOP [UNSPEC_SME_BMOPA UNSPEC_SME_BMOPS]) (define_int_iterator SME_BINARY_SLICE_SDI [UNSPEC_SME_ADD UNSPEC_SME_SUB]) @@ -4507,6 +4562,8 @@ (UNSPEC_SME_FMLA "fmla") (UNSPEC_SME_FMLAL "fmlal") (UNSPEC_SME_FMLS "fmls") + (UNSPEC_SME_FMOP4A "fmop4a") + (UNSPEC_SME_FMOP4S "fmop4s") (UNSPEC_SME_FMOPA "fmopa") (UNSPEC_SME_FMOPS "fmops") (UNSPEC_SME_FSUB "fsub") @@ -4520,6 +4577,8 @@ (UNSPEC_SME_SVDOT "svdot") (UNSPEC_SME_SMLA "smla") (UNSPEC_SME_SMLS "smls") + (UNSPEC_SME_SMOP4A "smop4a") + (UNSPEC_SME_SMOP4S "smop4s") (UNSPEC_SME_SMOPA "smopa") (UNSPEC_SME_SMOPS "smops") (UNSPEC_SME_ST1_HOR "st1_hor") @@ -4528,16 +4587,22 @@ (UNSPEC_SME_SUB_WRITE "sub_write") (UNSPEC_SME_SUDOT "sudot") (UNSPEC_SME_SUVDOT "suvdot") + (UNSPEC_SME_SUMOP4A "sumop4a") + (UNSPEC_SME_SUMOP4S "sumop4s") (UNSPEC_SME_SUMOPA "sumopa") (UNSPEC_SME_SUMOPS "sumops") (UNSPEC_SME_UDOT "udot") (UNSPEC_SME_UVDOT "uvdot") (UNSPEC_SME_UMLA "umla") (UNSPEC_SME_UMLS "umls") + (UNSPEC_SME_UMOP4A "umop4a") + (UNSPEC_SME_UMOP4S "umop4s") (UNSPEC_SME_UMOPA "umopa") (UNSPEC_SME_UMOPS "umops") (UNSPEC_SME_USDOT "usdot") (UNSPEC_SME_USVDOT "usvdot") + (UNSPEC_SME_USMOP4A "usmop4a") + (UNSPEC_SME_USMOP4S "usmop4s") (UNSPEC_SME_USMOPA "usmopa") (UNSPEC_SME_USMOPS "usmops") (UNSPEC_SME_WRITE_HOR "write_hor") diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h index c81bf074c501..d06e8def9376 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h @@ -68,7 +68,7 @@ #define TEST_DUAL_ZA(NAME, TYPE1, TYPE2, CODE1, CODE2) \ PROTO (NAME, void, (TYPE1 z0, TYPE1 z1, TYPE1 z2, TYPE1 z3, \ TYPE2 z4, TYPE2 z5, TYPE2 z6, TYPE2 z7, \ - svbool_t p0, svbool_t p1)) \ + svbool_t p0, svbool_t p1, fpm_t fpm0)) \ { \ INVOKE (CODE1, CODE2); \ } diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c new file mode 100644 index 000000000000..c2ccac3dcc23 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za16_bf16_bf16_0: +** ... +** bfmop4a za0\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za16_bf16_bf16_0, svbfloat16_t, + svmop4a_1x1_za16_bf16_bf16 (0, z0, z1), + svmop4a_za16 (0, z0, z1)); + +/* +** mop4a_1x1_za16_bf16_bf16_1: +** ... +** bfmop4a za1\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za16_bf16_bf16_1, svbfloat16_t, + svmop4a_1x1_za16_bf16_bf16 (1, z0, z1), + svmop4a_za16 (1, z0, z1)); + +/* +** mop4a_1x2_za16_bf16_bf16_0: +** ... +** bfmop4a za0\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za16_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t, + svmop4a_1x2_za16_bf16_bf16 (0, z0, z4), + svmop4a_za16 (0, z0, z4)); + +/* +** mop4a_1x2_za16_bf16_bf16_1: +** ... +** bfmop4a za1\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za16_bf16_bf16_1, svbfloat16_t, svbfloat16x2_t, + svmop4a_1x2_za16_bf16_bf16 (1, z0, z4), + svmop4a_za16 (1, z0, z4)); + +/* +** mop4a_2x1_za16_bf16_bf16_0: +** ... +** bfmop4a za0\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za16_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t, + svmop4a_2x1_za16_bf16_bf16 (0, z0, z4), + svmop4a_za16 (0, z0, z4)); + +/* +** mop4a_2x1_za16_bf16_bf16_1: +** ... +** bfmop4a za1\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za16_bf16_bf16_1, svbfloat16x2_t, svbfloat16_t, + svmop4a_2x1_za16_bf16_bf16 (1, z0, z4), + svmop4a_za16 (1, z0, z4)); + +/* +** mop4a_2x2_za16_bf16_bf16_0: +** ... +** bfmop4a za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za16_bf16_bf16_0, svbfloat16x2_t, + svmop4a_2x2_za16_bf16_bf16 (0, z0, z1), + svmop4a_za16 (0, z0, z1)); + +/* +** mop4a_2x2_za16_bf16_bf16_1: +** ... +** bfmop4a za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za16_bf16_bf16_1, svbfloat16x2_t, + svmop4a_2x2_za16_bf16_bf16 (1, z0, z1), + svmop4a_za16 (1, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c new file mode 100644 index 000000000000..a97caacb4542 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za16_f16_f16_0: +** ... +** fmop4a za0\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za16_f16_f16_0, svfloat16_t, + svmop4a_1x1_za16_f16_f16 (0, z0, z1), + svmop4a_za16 (0, z0, z1)); + +/* +** mop4a_1x1_za16_f16_f16_1: +** ... +** fmop4a za1\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za16_f16_f16_1, svfloat16_t, + svmop4a_1x1_za16_f16_f16 (1, z0, z1), + svmop4a_za16 (1, z0, z1)); + +/* +** mop4a_1x2_za16_f16_f16_0: +** ... +** fmop4a za0\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za16_f16_f16_0, svfloat16_t, svfloat16x2_t, + svmop4a_1x2_za16_f16_f16 (0, z0, z4), + svmop4a_za16 (0, z0, z4)); + +/* +** mop4a_1x2_za16_f16_f16_1: +** ... +** fmop4a za1\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za16_f16_f16_1, svfloat16_t, svfloat16x2_t, + svmop4a_1x2_za16_f16_f16 (1, z0, z4), + svmop4a_za16 (1, z0, z4)); + +/* +** mop4a_2x1_za16_f16_f16_0: +** ... +** fmop4a za0\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za16_f16_f16_0, svfloat16x2_t, svfloat16_t, + svmop4a_2x1_za16_f16_f16 (0, z0, z4), + svmop4a_za16 (0, z0, z4)); + +/* +** mop4a_2x1_za16_f16_f16_1: +** ... +** fmop4a za1\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za16_f16_f16_1, svfloat16x2_t, svfloat16_t, + svmop4a_2x1_za16_f16_f16 (1, z0, z4), + svmop4a_za16 (1, z0, z4)); + +/* +** mop4a_2x2_za16_f16_f16_0: +** ... +** fmop4a za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za16_f16_f16_0, svfloat16x2_t, + svmop4a_2x2_za16_f16_f16 (0, z0, z1), + svmop4a_za16 (0, z0, z1)); + +/* +** mop4a_2x2_za16_f16_f16_1: +** ... +** fmop4a za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za16_f16_f16_1, svfloat16x2_t, + svmop4a_2x2_za16_f16_f16 (1, z0, z1), + svmop4a_za16 (1, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c new file mode 100644 index 000000000000..01a5afd99ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f8f16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za16_mf8_mf8_0: +** ... +** fmop4a za0\.h, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za16_mf8_mf8_0, svmfloat8_t, + svmop4a_1x1_za16_mf8_mf8_fpm (0, z0, z1, fpm0), + svmop4a_za16_fpm (0, z0, z1, fpm0)); + +/* +** mop4a_1x1_za16_mf8_mf8_1: +** ... +** fmop4a za1\.h, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za16_mf8_mf8_1, svmfloat8_t, + svmop4a_1x1_za16_mf8_mf8_fpm (1, z0, z1, fpm0), + svmop4a_za16_fpm (1, z0, z1, fpm0)); + +/* +** mop4a_1x2_za16_mf8_mf8_0: +** ... +** fmop4a za0\.h, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za16_mf8_mf8_0, svmfloat8_t, svmfloat8x2_t, + svmop4a_1x2_za16_mf8_mf8_fpm (0, z0, z4, fpm0), + svmop4a_za16_fpm (0, z0, z4, fpm0)); + +/* +** mop4a_1x2_za16_mf8_mf8_1: +** ... +** fmop4a za1\.h, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za16_mf8_mf8_1, svmfloat8_t, svmfloat8x2_t, + svmop4a_1x2_za16_mf8_mf8_fpm (1, z0, z4, fpm0), + svmop4a_za16_fpm (1, z0, z4, fpm0)); + +/* +** mop4a_2x1_za16_mf8_mf8_0: +** ... +** fmop4a za0\.h, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za16_mf8_mf8_0, svmfloat8x2_t, svmfloat8_t, + svmop4a_2x1_za16_mf8_mf8_fpm (0, z0, z4, fpm0), + svmop4a_za16_fpm (0, z0, z4, fpm0)); + +/* +** mop4a_2x1_za16_mf8_mf8_1: +** ... +** fmop4a za1\.h, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za16_mf8_mf8_1, svmfloat8x2_t, svmfloat8_t, + svmop4a_2x1_za16_mf8_mf8_fpm (1, z0, z4, fpm0), + svmop4a_za16_fpm (1, z0, z4, fpm0)); + +/* +** mop4a_2x2_za16_mf8_mf8_0: +** ... +** fmop4a za0\.h, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za16_mf8_mf8_0, svmfloat8x2_t, + svmop4a_2x2_za16_mf8_mf8_fpm (0, z0, z1, fpm0), + svmop4a_za16_fpm (0, z0, z1, fpm0)); + +/* +** mop4a_2x2_za16_mf8_mf8_1: +** ... +** fmop4a za1\.h, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za16_mf8_mf8_1, svmfloat8x2_t, + svmop4a_2x2_za16_mf8_mf8_fpm (1, z0, z1, fpm0), + svmop4a_za16_fpm (1, z0, z1, fpm0)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c new file mode 100644 index 000000000000..29f34252d317 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_bf16_bf16_0: +** ... +** bfmop4a za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_bf16_bf16_0, svbfloat16_t, + svmop4a_1x1_za32_bf16_bf16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_1x1_za32_bf16_bf16_3: +** ... +** bfmop4a za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_bf16_bf16_3, svbfloat16_t, + svmop4a_1x1_za32_bf16_bf16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); + +/* +** mop4a_1x2_za32_bf16_bf16_0: +** ... +** bfmop4a za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t, + svmop4a_1x2_za32_bf16_bf16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_bf16_bf16_3: +** ... +** bfmop4a za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_bf16_bf16_3, svbfloat16_t, svbfloat16x2_t, + svmop4a_1x2_za32_bf16_bf16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_bf16_bf16_0: +** ... +** bfmop4a za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t, + svmop4a_2x1_za32_bf16_bf16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_bf16_bf16_3: +** ... +** bfmop4a za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_bf16_bf16_3, svbfloat16x2_t, svbfloat16_t, + svmop4a_2x1_za32_bf16_bf16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_bf16_bf16_0: +** ... +** bfmop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_bf16_bf16_0, svbfloat16x2_t, + svmop4a_2x2_za32_bf16_bf16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_2x2_za32_bf16_bf16_3: +** ... +** bfmop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_bf16_bf16_3, svbfloat16x2_t, + svmop4a_2x2_za32_bf16_bf16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c new file mode 100644 index 000000000000..88e23597e9b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_f16_f16_0: +** ... +** fmop4a za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_f16_f16_0, svfloat16_t, + svmop4a_1x1_za32_f16_f16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_1x1_za32_f16_f16_3: +** ... +** fmop4a za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_f16_f16_3, svfloat16_t, + svmop4a_1x1_za32_f16_f16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); + +/* +** mop4a_1x2_za32_f16_f16_0: +** ... +** fmop4a za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_f16_f16_0, svfloat16_t, svfloat16x2_t, + svmop4a_1x2_za32_f16_f16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_f16_f16_3: +** ... +** fmop4a za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_f16_f16_3, svfloat16_t, svfloat16x2_t, + svmop4a_1x2_za32_f16_f16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_f16_f16_0: +** ... +** fmop4a za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_f16_f16_0, svfloat16x2_t, svfloat16_t, + svmop4a_2x1_za32_f16_f16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_f16_f16_3: +** ... +** fmop4a za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_f16_f16_3, svfloat16x2_t, svfloat16_t, + svmop4a_2x1_za32_f16_f16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_f16_f16_0: +** ... +** fmop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_f16_f16_0, svfloat16x2_t, + svmop4a_2x2_za32_f16_f16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_2x2_za32_f16_f16_3: +** ... +** fmop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_f16_f16_3, svfloat16x2_t, + svmop4a_2x2_za32_f16_f16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c new file mode 100644 index 000000000000..9a5728378676 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_f32_f32_0: +** ... +** fmop4a za0\.s, z0\.s, z30\.s +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_f32_f32_0, svfloat32_t, + svmop4a_1x1_za32_f32_f32 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_1x1_za32_f32_f32_3: +** ... +** fmop4a za3\.s, z0\.s, z30\.s +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_f32_f32_3, svfloat32_t, + svmop4a_1x1_za32_f32_f32 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); + +/* +** mop4a_1x2_za32_f32_f32_0: +** ... +** fmop4a za0\.s, z0\.s, {z30\.s - z31\.s} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_f32_f32_0, svfloat32_t, svfloat32x2_t, + svmop4a_1x2_za32_f32_f32 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_f32_f32_3: +** ... +** fmop4a za3\.s, z0\.s, {z30\.s - z31\.s} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_f32_f32_3, svfloat32_t, svfloat32x2_t, + svmop4a_1x2_za32_f32_f32 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_f32_f32_0: +** ... +** fmop4a za0\.s, {z0\.s - z1\.s}, z30\.s +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_f32_f32_0, svfloat32x2_t, svfloat32_t, + svmop4a_2x1_za32_f32_f32 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_f32_f32_3: +** ... +** fmop4a za3\.s, {z0\.s - z1\.s}, z30\.s +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_f32_f32_3, svfloat32x2_t, svfloat32_t, + svmop4a_2x1_za32_f32_f32 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_f32_f32_0: +** ... +** fmop4a za0\.s, {z0\.s - z1\.s}, {z30\.s - z31\.s} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_f32_f32_0, svfloat32x2_t, + svmop4a_2x2_za32_f32_f32 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_2x2_za32_f32_f32_3: +** ... +** fmop4a za3\.s, {z0\.s - z1\.s}, {z30\.s - z31\.s} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_f32_f32_3, svfloat32x2_t, + svmop4a_2x2_za32_f32_f32 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c new file mode 100644 index 000000000000..635ce7b20bc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f8f32" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_mf8_mf8_0: +** ... +** fmop4a za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_mf8_mf8_0, svmfloat8_t, + svmop4a_1x1_za32_mf8_mf8_fpm (0, z0, z1, fpm0), + svmop4a_za32_fpm (0, z0, z1, fpm0)); + +/* +** mop4a_1x1_za32_mf8_mf8_3: +** ... +** fmop4a za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_mf8_mf8_3, svmfloat8_t, + svmop4a_1x1_za32_mf8_mf8_fpm (3, z0, z1, fpm0), + svmop4a_za32_fpm (3, z0, z1, fpm0)); + +/* +** mop4a_1x2_za32_mf8_mf8_0: +** ... +** fmop4a za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_mf8_mf8_0, svmfloat8_t, svmfloat8x2_t, + svmop4a_1x2_za32_mf8_mf8_fpm (0, z0, z4, fpm0), + svmop4a_za32_fpm (0, z0, z4, fpm0)); + +/* +** mop4a_1x2_za32_mf8_mf8_3: +** ... +** fmop4a za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_mf8_mf8_3, svmfloat8_t, svmfloat8x2_t, + svmop4a_1x2_za32_mf8_mf8_fpm (3, z0, z4, fpm0), + svmop4a_za32_fpm (3, z0, z4, fpm0)); + +/* +** mop4a_2x1_za32_mf8_mf8_0: +** ... +** fmop4a za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_mf8_mf8_0, svmfloat8x2_t, svmfloat8_t, + svmop4a_2x1_za32_mf8_mf8_fpm (0, z0, z4, fpm0), + svmop4a_za32_fpm (0, z0, z4, fpm0)); + +/* +** mop4a_2x1_za32_mf8_mf8_3: +** ... +** fmop4a za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_mf8_mf8_3, svmfloat8x2_t, svmfloat8_t, + svmop4a_2x1_za32_mf8_mf8_fpm (3, z0, z4, fpm0), + svmop4a_za32_fpm (3, z0, z4, fpm0)); + +/* +** mop4a_2x2_za32_mf8_mf8_0: +** ... +** fmop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_mf8_mf8_0, svmfloat8x2_t, + svmop4a_2x2_za32_mf8_mf8_fpm (0, z0, z1, fpm0), + svmop4a_za32_fpm (0, z0, z1, fpm0)); + +/* +** mop4a_2x2_za32_mf8_mf8_3: +** ... +** fmop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_mf8_mf8_3, svmfloat8x2_t, + svmop4a_2x2_za32_mf8_mf8_fpm (3, z0, z1, fpm0), + svmop4a_za32_fpm (3, z0, z1, fpm0)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c new file mode 100644 index 000000000000..9b989ab550cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_s16_s16_0: +** ... +** smop4a za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_s16_s16_0, svint16_t, + svmop4a_1x1_za32_s16_s16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_1x1_za32_s16_s16_3: +** ... +** smop4a za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_s16_s16_3, svint16_t, + svmop4a_1x1_za32_s16_s16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); + +/* +** mop4a_1x2_za32_s16_s16_0: +** ... +** smop4a za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_s16_s16_0, svint16_t, svint16x2_t, + svmop4a_1x2_za32_s16_s16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_s16_s16_3: +** ... +** smop4a za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_s16_s16_3, svint16_t, svint16x2_t, + svmop4a_1x2_za32_s16_s16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_s16_s16_0: +** ... +** smop4a za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_s16_s16_0, svint16x2_t, svint16_t, + svmop4a_2x1_za32_s16_s16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_s16_s16_3: +** ... +** smop4a za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_s16_s16_3, svint16x2_t, svint16_t, + svmop4a_2x1_za32_s16_s16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_s16_s16_0: +** ... +** smop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_s16_s16_0, svint16x2_t, + svmop4a_2x2_za32_s16_s16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_2x2_za32_s16_s16_3: +** ... +** smop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_s16_s16_3, svint16x2_t, + svmop4a_2x2_za32_s16_s16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c new file mode 100644 index 000000000000..cd40365a70ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_s8_s8_0: +** ... +** smop4a za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_s8_s8_0, svint8_t, + svmop4a_1x1_za32_s8_s8 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_1x1_za32_s8_s8_3: +** ... +** smop4a za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_s8_s8_3, svint8_t, + svmop4a_1x1_za32_s8_s8 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); + +/* +** mop4a_1x2_za32_s8_s8_0: +** ... +** smop4a za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_s8_s8_0, svint8_t, svint8x2_t, + svmop4a_1x2_za32_s8_s8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_s8_s8_3: +** ... +** smop4a za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_s8_s8_3, svint8_t, svint8x2_t, + svmop4a_1x2_za32_s8_s8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_s8_s8_0: +** ... +** smop4a za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_s8_s8_0, svint8x2_t, svint8_t, + svmop4a_2x1_za32_s8_s8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_s8_s8_3: +** ... +** smop4a za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_s8_s8_3, svint8x2_t, svint8_t, + svmop4a_2x1_za32_s8_s8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_s8_s8_0: +** ... +** smop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_s8_s8_0, svint8x2_t, + svmop4a_2x2_za32_s8_s8 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_2x2_za32_s8_s8_3: +** ... +** smop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_s8_s8_3, svint8x2_t, + svmop4a_2x2_za32_s8_s8 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c new file mode 100644 index 000000000000..0e23824fdf95 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_s8_u8_0: +** ... +** sumop4a za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za32_s8_u8_0, svint8_t, svuint8_t, + svmop4a_1x1_za32_s8_u8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x1_za32_s8_u8_3: +** ... +** sumop4a za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za32_s8_u8_3, svint8_t, svuint8_t, + svmop4a_1x1_za32_s8_u8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_1x2_za32_s8_u8_0: +** ... +** sumop4a za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_s8_u8_0, svint8_t, svuint8x2_t, + svmop4a_1x2_za32_s8_u8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_s8_u8_3: +** ... +** sumop4a za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_s8_u8_3, svint8_t, svuint8x2_t, + svmop4a_1x2_za32_s8_u8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_s8_u8_0: +** ... +** sumop4a za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_s8_u8_0, svint8x2_t, svuint8_t, + svmop4a_2x1_za32_s8_u8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_s8_u8_3: +** ... +** sumop4a za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_s8_u8_3, svint8x2_t, svuint8_t, + svmop4a_2x1_za32_s8_u8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_s8_u8_0: +** ... +** sumop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za32_s8_u8_0, svint8x2_t, svuint8x2_t, + svmop4a_2x2_za32_s8_u8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x2_za32_s8_u8_3: +** ... +** sumop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za32_s8_u8_3, svint8x2_t, svuint8x2_t, + svmop4a_2x2_za32_s8_u8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c new file mode 100644 index 000000000000..b082abc5bbc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_u16_u16_0: +** ... +** umop4a za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_u16_u16_0, svuint16_t, + svmop4a_1x1_za32_u16_u16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_1x1_za32_u16_u16_3: +** ... +** umop4a za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_u16_u16_3, svuint16_t, + svmop4a_1x1_za32_u16_u16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); + +/* +** mop4a_1x2_za32_u16_u16_0: +** ... +** umop4a za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_u16_u16_0, svuint16_t, svuint16x2_t, + svmop4a_1x2_za32_u16_u16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_u16_u16_3: +** ... +** umop4a za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_u16_u16_3, svuint16_t, svuint16x2_t, + svmop4a_1x2_za32_u16_u16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_u16_u16_0: +** ... +** umop4a za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_u16_u16_0, svuint16x2_t, svuint16_t, + svmop4a_2x1_za32_u16_u16 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_u16_u16_3: +** ... +** umop4a za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_u16_u16_3, svuint16x2_t, svuint16_t, + svmop4a_2x1_za32_u16_u16 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_u16_u16_0: +** ... +** umop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_u16_u16_0, svuint16x2_t, + svmop4a_2x2_za32_u16_u16 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_2x2_za32_u16_u16_3: +** ... +** umop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_u16_u16_3, svuint16x2_t, + svmop4a_2x2_za32_u16_u16 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c new file mode 100644 index 000000000000..c6ace5172081 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_u8_s8_0: +** ... +** usmop4a za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za32_u8_s8_0, svuint8_t, svint8_t, + svmop4a_1x1_za32_u8_s8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x1_za32_u8_s8_3: +** ... +** usmop4a za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za32_u8_s8_3, svuint8_t, svint8_t, + svmop4a_1x1_za32_u8_s8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_1x2_za32_u8_s8_0: +** ... +** usmop4a za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_u8_s8_0, svuint8_t, svint8x2_t, + svmop4a_1x2_za32_u8_s8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_u8_s8_3: +** ... +** usmop4a za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_u8_s8_3, svuint8_t, svint8x2_t, + svmop4a_1x2_za32_u8_s8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_u8_s8_0: +** ... +** usmop4a za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_u8_s8_0, svuint8x2_t, svint8_t, + svmop4a_2x1_za32_u8_s8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_u8_s8_3: +** ... +** usmop4a za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_u8_s8_3, svuint8x2_t, svint8_t, + svmop4a_2x1_za32_u8_s8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_u8_s8_0: +** ... +** usmop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za32_u8_s8_0, svuint8x2_t, svint8x2_t, + svmop4a_2x2_za32_u8_s8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x2_za32_u8_s8_3: +** ... +** usmop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za32_u8_s8_3, svuint8x2_t, svint8x2_t, + svmop4a_2x2_za32_u8_s8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c new file mode 100644 index 000000000000..381730b20a85 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za32_u8_u8_0: +** ... +** umop4a za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_u8_u8_0, svuint8_t, + svmop4a_1x1_za32_u8_u8 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_1x1_za32_u8_u8_3: +** ... +** umop4a za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za32_u8_u8_3, svuint8_t, + svmop4a_1x1_za32_u8_u8 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); + +/* +** mop4a_1x2_za32_u8_u8_0: +** ... +** umop4a za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_u8_u8_0, svuint8_t, svuint8x2_t, + svmop4a_1x2_za32_u8_u8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_1x2_za32_u8_u8_3: +** ... +** umop4a za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za32_u8_u8_3, svuint8_t, svuint8x2_t, + svmop4a_1x2_za32_u8_u8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x1_za32_u8_u8_0: +** ... +** umop4a za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_u8_u8_0, svuint8x2_t, svuint8_t, + svmop4a_2x1_za32_u8_u8 (0, z0, z4), + svmop4a_za32 (0, z0, z4)); + +/* +** mop4a_2x1_za32_u8_u8_3: +** ... +** umop4a za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za32_u8_u8_3, svuint8x2_t, svuint8_t, + svmop4a_2x1_za32_u8_u8 (3, z0, z4), + svmop4a_za32 (3, z0, z4)); + +/* +** mop4a_2x2_za32_u8_u8_0: +** ... +** umop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_u8_u8_0, svuint8x2_t, + svmop4a_2x2_za32_u8_u8 (0, z0, z1), + svmop4a_za32 (0, z0, z1)); + +/* +** mop4a_2x2_za32_u8_u8_3: +** ... +** umop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za32_u8_u8_3, svuint8x2_t, + svmop4a_2x2_za32_u8_u8 (3, z0, z1), + svmop4a_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c new file mode 100644 index 000000000000..6a9579ce4ae0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f64f64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za64_f64_f64_0: +** ... +** fmop4a za0\.d, z0\.d, z30\.d +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za64_f64_f64_0, svfloat64_t, + svmop4a_1x1_za64_f64_f64 (0, z0, z1), + svmop4a_za64 (0, z0, z1)); + +/* +** mop4a_1x1_za64_f64_f64_7: +** ... +** fmop4a za7\.d, z0\.d, z30\.d +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za64_f64_f64_7, svfloat64_t, + svmop4a_1x1_za64_f64_f64 (7, z0, z1), + svmop4a_za64 (7, z0, z1)); + +/* +** mop4a_1x2_za64_f64_f64_0: +** ... +** fmop4a za0\.d, z0\.d, {z30\.d - z31\.d} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_f64_f64_0, svfloat64_t, svfloat64x2_t, + svmop4a_1x2_za64_f64_f64 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_1x2_za64_f64_f64_7: +** ... +** fmop4a za7\.d, z0\.d, {z30\.d - z31\.d} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_f64_f64_7, svfloat64_t, svfloat64x2_t, + svmop4a_1x2_za64_f64_f64 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x1_za64_f64_f64_0: +** ... +** fmop4a za0\.d, {z0\.d - z1\.d}, z30\.d +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_f64_f64_0, svfloat64x2_t, svfloat64_t, + svmop4a_2x1_za64_f64_f64 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_2x1_za64_f64_f64_7: +** ... +** fmop4a za7\.d, {z0\.d - z1\.d}, z30\.d +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_f64_f64_7, svfloat64x2_t, svfloat64_t, + svmop4a_2x1_za64_f64_f64 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x2_za64_f64_f64_0: +** ... +** fmop4a za0\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za64_f64_f64_0, svfloat64x2_t, + svmop4a_2x2_za64_f64_f64 (0, z0, z1), + svmop4a_za64 (0, z0, z1)); + +/* +** mop4a_2x2_za64_f64_f64_7: +** ... +** fmop4a za7\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za64_f64_f64_7, svfloat64x2_t, + svmop4a_2x2_za64_f64_f64 (7, z0, z1), + svmop4a_za64 (7, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c new file mode 100644 index 000000000000..37dd2fb4bfdb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za64_s16_s16_0: +** ... +** smop4a za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za64_s16_s16_0, svint16_t, + svmop4a_1x1_za64_s16_s16 (0, z0, z1), + svmop4a_za64 (0, z0, z1)); + +/* +** mop4a_1x1_za64_s16_s16_7: +** ... +** smop4a za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za64_s16_s16_7, svint16_t, + svmop4a_1x1_za64_s16_s16 (7, z0, z1), + svmop4a_za64 (7, z0, z1)); + +/* +** mop4a_1x2_za64_s16_s16_0: +** ... +** smop4a za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_s16_s16_0, svint16_t, svint16x2_t, + svmop4a_1x2_za64_s16_s16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_1x2_za64_s16_s16_7: +** ... +** smop4a za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_s16_s16_7, svint16_t, svint16x2_t, + svmop4a_1x2_za64_s16_s16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x1_za64_s16_s16_0: +** ... +** smop4a za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_s16_s16_0, svint16x2_t, svint16_t, + svmop4a_2x1_za64_s16_s16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_2x1_za64_s16_s16_7: +** ... +** smop4a za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_s16_s16_7, svint16x2_t, svint16_t, + svmop4a_2x1_za64_s16_s16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x2_za64_s16_s16_0: +** ... +** smop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za64_s16_s16_0, svint16x2_t, + svmop4a_2x2_za64_s16_s16 (0, z0, z1), + svmop4a_za64 (0, z0, z1)); + +/* +** mop4a_2x2_za64_s16_s16_7: +** ... +** smop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za64_s16_s16_7, svint16x2_t, + svmop4a_2x2_za64_s16_s16 (7, z0, z1), + svmop4a_za64 (7, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c new file mode 100644 index 000000000000..fe234c9b174d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za64_s16_u16_0: +** ... +** sumop4a za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za64_s16_u16_0, svint16_t, svuint16_t, + svmop4a_1x1_za64_s16_u16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_1x1_za64_s16_u16_7: +** ... +** sumop4a za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za64_s16_u16_7, svint16_t, svuint16_t, + svmop4a_1x1_za64_s16_u16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_1x2_za64_s16_u16_0: +** ... +** sumop4a za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_s16_u16_0, svint16_t, svuint16x2_t, + svmop4a_1x2_za64_s16_u16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_1x2_za64_s16_u16_7: +** ... +** sumop4a za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_s16_u16_7, svint16_t, svuint16x2_t, + svmop4a_1x2_za64_s16_u16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x1_za64_s16_u16_0: +** ... +** sumop4a za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_s16_u16_0, svint16x2_t, svuint16_t, + svmop4a_2x1_za64_s16_u16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_2x1_za64_s16_u16_7: +** ... +** sumop4a za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_s16_u16_7, svint16x2_t, svuint16_t, + svmop4a_2x1_za64_s16_u16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x2_za64_s16_u16_0: +** ... +** sumop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za64_s16_u16_0, svint16x2_t, svuint16x2_t, + svmop4a_2x2_za64_s16_u16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_2x2_za64_s16_u16_7: +** ... +** sumop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za64_s16_u16_7, svint16x2_t, svuint16x2_t, + svmop4a_2x2_za64_s16_u16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c new file mode 100644 index 000000000000..f6f9a10434b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za64_u16_s16_0: +** ... +** usmop4a za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za64_u16_s16_0, svuint16_t, svint16_t, + svmop4a_1x1_za64_u16_s16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_1x1_za64_u16_s16_7: +** ... +** usmop4a za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_1x1_za64_u16_s16_7, svuint16_t, svint16_t, + svmop4a_1x1_za64_u16_s16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_1x2_za64_u16_s16_0: +** ... +** usmop4a za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_u16_s16_0, svuint16_t, svint16x2_t, + svmop4a_1x2_za64_u16_s16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_1x2_za64_u16_s16_7: +** ... +** usmop4a za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_u16_s16_7, svuint16_t, svint16x2_t, + svmop4a_1x2_za64_u16_s16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x1_za64_u16_s16_0: +** ... +** usmop4a za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_u16_s16_0, svuint16x2_t, svint16_t, + svmop4a_2x1_za64_u16_s16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_2x1_za64_u16_s16_7: +** ... +** usmop4a za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_u16_s16_7, svuint16x2_t, svint16_t, + svmop4a_2x1_za64_u16_s16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x2_za64_u16_s16_0: +** ... +** usmop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za64_u16_s16_0, svuint16x2_t, svint16x2_t, + svmop4a_2x2_za64_u16_s16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_2x2_za64_u16_s16_7: +** ... +** usmop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_2x2_za64_u16_s16_7, svuint16x2_t, svint16x2_t, + svmop4a_2x2_za64_u16_s16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c new file mode 100644 index 000000000000..0ab6743dafd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4a_1x1_za64_u16_u16_0: +** ... +** umop4a za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za64_u16_u16_0, svuint16_t, + svmop4a_1x1_za64_u16_u16 (0, z0, z1), + svmop4a_za64 (0, z0, z1)); + +/* +** mop4a_1x1_za64_u16_u16_7: +** ... +** umop4a za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4a_1x1_za64_u16_u16_7, svuint16_t, + svmop4a_1x1_za64_u16_u16 (7, z0, z1), + svmop4a_za64 (7, z0, z1)); + +/* +** mop4a_1x2_za64_u16_u16_0: +** ... +** umop4a za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_u16_u16_0, svuint16_t, svuint16x2_t, + svmop4a_1x2_za64_u16_u16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_1x2_za64_u16_u16_7: +** ... +** umop4a za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4a_1x2_za64_u16_u16_7, svuint16_t, svuint16x2_t, + svmop4a_1x2_za64_u16_u16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x1_za64_u16_u16_0: +** ... +** umop4a za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_u16_u16_0, svuint16x2_t, svuint16_t, + svmop4a_2x1_za64_u16_u16 (0, z0, z4), + svmop4a_za64 (0, z0, z4)); + +/* +** mop4a_2x1_za64_u16_u16_7: +** ... +** umop4a za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4a_2x1_za64_u16_u16_7, svuint16x2_t, svuint16_t, + svmop4a_2x1_za64_u16_u16 (7, z0, z4), + svmop4a_za64 (7, z0, z4)); + +/* +** mop4a_2x2_za64_u16_u16_0: +** ... +** umop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za64_u16_u16_0, svuint16x2_t, + svmop4a_2x2_za64_u16_u16 (0, z0, z1), + svmop4a_za64 (0, z0, z1)); + +/* +** mop4a_2x2_za64_u16_u16_7: +** ... +** umop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4a_2x2_za64_u16_u16_7, svuint16x2_t, + svmop4a_2x2_za64_u16_u16 (7, z0, z1), + svmop4a_za64 (7, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c new file mode 100644 index 000000000000..4d0ad9af55e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za16_bf16_bf16_0: +** ... +** bfmop4s za0\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za16_bf16_bf16_0, svbfloat16_t, + svmop4s_1x1_za16_bf16_bf16 (0, z0, z1), + svmop4s_za16 (0, z0, z1)); + +/* +** mop4s_1x1_za16_bf16_bf16_1: +** ... +** bfmop4s za1\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za16_bf16_bf16_1, svbfloat16_t, + svmop4s_1x1_za16_bf16_bf16 (1, z0, z1), + svmop4s_za16 (1, z0, z1)); + +/* +** mop4s_1x2_za16_bf16_bf16_0: +** ... +** bfmop4s za0\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za16_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t, + svmop4s_1x2_za16_bf16_bf16 (0, z0, z4), + svmop4s_za16 (0, z0, z4)); + +/* +** mop4s_1x2_za16_bf16_bf16_1: +** ... +** bfmop4s za1\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za16_bf16_bf16_1, svbfloat16_t, svbfloat16x2_t, + svmop4s_1x2_za16_bf16_bf16 (1, z0, z4), + svmop4s_za16 (1, z0, z4)); + +/* +** mop4s_2x1_za16_bf16_bf16_0: +** ... +** bfmop4s za0\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za16_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t, + svmop4s_2x1_za16_bf16_bf16 (0, z0, z4), + svmop4s_za16 (0, z0, z4)); + +/* +** mop4s_2x1_za16_bf16_bf16_1: +** ... +** bfmop4s za1\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za16_bf16_bf16_1, svbfloat16x2_t, svbfloat16_t, + svmop4s_2x1_za16_bf16_bf16 (1, z0, z4), + svmop4s_za16 (1, z0, z4)); + +/* +** mop4s_2x2_za16_bf16_bf16_0: +** ... +** bfmop4s za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za16_bf16_bf16_0, svbfloat16x2_t, + svmop4s_2x2_za16_bf16_bf16 (0, z0, z1), + svmop4s_za16 (0, z0, z1)); + +/* +** mop4s_2x2_za16_bf16_bf16_1: +** ... +** bfmop4s za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za16_bf16_bf16_1, svbfloat16x2_t, + svmop4s_2x2_za16_bf16_bf16 (1, z0, z1), + svmop4s_za16 (1, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c new file mode 100644 index 000000000000..8866b67d5c6b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za16_f16_f16_0: +** ... +** fmop4s za0\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za16_f16_f16_0, svfloat16_t, + svmop4s_1x1_za16_f16_f16 (0, z0, z1), + svmop4s_za16 (0, z0, z1)); + +/* +** mop4s_1x1_za16_f16_f16_1: +** ... +** fmop4s za1\.h, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za16_f16_f16_1, svfloat16_t, + svmop4s_1x1_za16_f16_f16 (1, z0, z1), + svmop4s_za16 (1, z0, z1)); + +/* +** mop4s_1x2_za16_f16_f16_0: +** ... +** fmop4s za0\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za16_f16_f16_0, svfloat16_t, svfloat16x2_t, + svmop4s_1x2_za16_f16_f16 (0, z0, z4), + svmop4s_za16 (0, z0, z4)); + +/* +** mop4s_1x2_za16_f16_f16_1: +** ... +** fmop4s za1\.h, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za16_f16_f16_1, svfloat16_t, svfloat16x2_t, + svmop4s_1x2_za16_f16_f16 (1, z0, z4), + svmop4s_za16 (1, z0, z4)); + +/* +** mop4s_2x1_za16_f16_f16_0: +** ... +** fmop4s za0\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za16_f16_f16_0, svfloat16x2_t, svfloat16_t, + svmop4s_2x1_za16_f16_f16 (0, z0, z4), + svmop4s_za16 (0, z0, z4)); + +/* +** mop4s_2x1_za16_f16_f16_1: +** ... +** fmop4s za1\.h, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za16_f16_f16_1, svfloat16x2_t, svfloat16_t, + svmop4s_2x1_za16_f16_f16 (1, z0, z4), + svmop4s_za16 (1, z0, z4)); + +/* +** mop4s_2x2_za16_f16_f16_0: +** ... +** fmop4s za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za16_f16_f16_0, svfloat16x2_t, + svmop4s_2x2_za16_f16_f16 (0, z0, z1), + svmop4s_za16 (0, z0, z1)); + +/* +** mop4s_2x2_za16_f16_f16_1: +** ... +** fmop4s za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za16_f16_f16_1, svfloat16x2_t, + svmop4s_2x2_za16_f16_f16 (1, z0, z1), + svmop4s_za16 (1, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c new file mode 100644 index 000000000000..f2c08dd06ce1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_bf16_bf16_0: +** ... +** bfmop4s za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_bf16_bf16_0, svbfloat16_t, + svmop4s_1x1_za32_bf16_bf16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_1x1_za32_bf16_bf16_3: +** ... +** bfmop4s za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_bf16_bf16_3, svbfloat16_t, + svmop4s_1x1_za32_bf16_bf16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); + +/* +** mop4s_1x2_za32_bf16_bf16_0: +** ... +** bfmop4s za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t, + svmop4s_1x2_za32_bf16_bf16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_bf16_bf16_3: +** ... +** bfmop4s za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_bf16_bf16_3, svbfloat16_t, svbfloat16x2_t, + svmop4s_1x2_za32_bf16_bf16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_bf16_bf16_0: +** ... +** bfmop4s za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t, + svmop4s_2x1_za32_bf16_bf16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_bf16_bf16_3: +** ... +** bfmop4s za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_bf16_bf16_3, svbfloat16x2_t, svbfloat16_t, + svmop4s_2x1_za32_bf16_bf16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_bf16_bf16_0: +** ... +** bfmop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_bf16_bf16_0, svbfloat16x2_t, + svmop4s_2x2_za32_bf16_bf16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_2x2_za32_bf16_bf16_3: +** ... +** bfmop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_bf16_bf16_3, svbfloat16x2_t, + svmop4s_2x2_za32_bf16_bf16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c new file mode 100644 index 000000000000..0da9d63cb3d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_f16_f16_0: +** ... +** fmop4s za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_f16_f16_0, svfloat16_t, + svmop4s_1x1_za32_f16_f16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_1x1_za32_f16_f16_3: +** ... +** fmop4s za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_f16_f16_3, svfloat16_t, + svmop4s_1x1_za32_f16_f16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); + +/* +** mop4s_1x2_za32_f16_f16_0: +** ... +** fmop4s za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_f16_f16_0, svfloat16_t, svfloat16x2_t, + svmop4s_1x2_za32_f16_f16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_f16_f16_3: +** ... +** fmop4s za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_f16_f16_3, svfloat16_t, svfloat16x2_t, + svmop4s_1x2_za32_f16_f16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_f16_f16_0: +** ... +** fmop4s za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_f16_f16_0, svfloat16x2_t, svfloat16_t, + svmop4s_2x1_za32_f16_f16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_f16_f16_3: +** ... +** fmop4s za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_f16_f16_3, svfloat16x2_t, svfloat16_t, + svmop4s_2x1_za32_f16_f16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_f16_f16_0: +** ... +** fmop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_f16_f16_0, svfloat16x2_t, + svmop4s_2x2_za32_f16_f16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_2x2_za32_f16_f16_3: +** ... +** fmop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_f16_f16_3, svfloat16x2_t, + svmop4s_2x2_za32_f16_f16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c new file mode 100644 index 000000000000..8692f188404f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_s16_s16_0: +** ... +** smop4s za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_s16_s16_0, svint16_t, + svmop4s_1x1_za32_s16_s16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_1x1_za32_s16_s16_3: +** ... +** smop4s za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_s16_s16_3, svint16_t, + svmop4s_1x1_za32_s16_s16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); + +/* +** mop4s_1x2_za32_s16_s16_0: +** ... +** smop4s za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_s16_s16_0, svint16_t, svint16x2_t, + svmop4s_1x2_za32_s16_s16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_s16_s16_3: +** ... +** smop4s za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_s16_s16_3, svint16_t, svint16x2_t, + svmop4s_1x2_za32_s16_s16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_s16_s16_0: +** ... +** smop4s za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_s16_s16_0, svint16x2_t, svint16_t, + svmop4s_2x1_za32_s16_s16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_s16_s16_3: +** ... +** smop4s za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_s16_s16_3, svint16x2_t, svint16_t, + svmop4s_2x1_za32_s16_s16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_s16_s16_0: +** ... +** smop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_s16_s16_0, svint16x2_t, + svmop4s_2x2_za32_s16_s16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_2x2_za32_s16_s16_3: +** ... +** smop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_s16_s16_3, svint16x2_t, + svmop4s_2x2_za32_s16_s16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c new file mode 100644 index 000000000000..0673c8b6d975 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_s8_s8_0: +** ... +** smop4s za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_s8_s8_0, svint8_t, + svmop4s_1x1_za32_s8_s8 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_1x1_za32_s8_s8_3: +** ... +** smop4s za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_s8_s8_3, svint8_t, + svmop4s_1x1_za32_s8_s8 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); + +/* +** mop4s_1x2_za32_s8_s8_0: +** ... +** smop4s za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_s8_s8_0, svint8_t, svint8x2_t, + svmop4s_1x2_za32_s8_s8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_s8_s8_3: +** ... +** smop4s za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_s8_s8_3, svint8_t, svint8x2_t, + svmop4s_1x2_za32_s8_s8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_s8_s8_0: +** ... +** smop4s za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_s8_s8_0, svint8x2_t, svint8_t, + svmop4s_2x1_za32_s8_s8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_s8_s8_3: +** ... +** smop4s za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_s8_s8_3, svint8x2_t, svint8_t, + svmop4s_2x1_za32_s8_s8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_s8_s8_0: +** ... +** smop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_s8_s8_0, svint8x2_t, + svmop4s_2x2_za32_s8_s8 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_2x2_za32_s8_s8_3: +** ... +** smop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_s8_s8_3, svint8x2_t, + svmop4s_2x2_za32_s8_s8 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c new file mode 100644 index 000000000000..da8e3ddb31d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_s8_u8_0: +** ... +** sumop4s za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za32_s8_u8_0, svint8_t, svuint8_t, + svmop4s_1x1_za32_s8_u8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x1_za32_s8_u8_3: +** ... +** sumop4s za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za32_s8_u8_3, svint8_t, svuint8_t, + svmop4s_1x1_za32_s8_u8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_1x2_za32_s8_u8_0: +** ... +** sumop4s za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_s8_u8_0, svint8_t, svuint8x2_t, + svmop4s_1x2_za32_s8_u8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_s8_u8_3: +** ... +** sumop4s za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_s8_u8_3, svint8_t, svuint8x2_t, + svmop4s_1x2_za32_s8_u8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_s8_u8_0: +** ... +** sumop4s za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_s8_u8_0, svint8x2_t, svuint8_t, + svmop4s_2x1_za32_s8_u8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_s8_u8_3: +** ... +** sumop4s za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_s8_u8_3, svint8x2_t, svuint8_t, + svmop4s_2x1_za32_s8_u8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_s8_u8_0: +** ... +** sumop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za32_s8_u8_0, svint8x2_t, svuint8x2_t, + svmop4s_2x2_za32_s8_u8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x2_za32_s8_u8_3: +** ... +** sumop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za32_s8_u8_3, svint8x2_t, svuint8x2_t, + svmop4s_2x2_za32_s8_u8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c new file mode 100644 index 000000000000..fdb19b617ecc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_u16_u16_0: +** ... +** umop4s za0\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_u16_u16_0, svuint16_t, + svmop4s_1x1_za32_u16_u16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_1x1_za32_u16_u16_3: +** ... +** umop4s za3\.s, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_u16_u16_3, svuint16_t, + svmop4s_1x1_za32_u16_u16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); + +/* +** mop4s_1x2_za32_u16_u16_0: +** ... +** umop4s za0\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_u16_u16_0, svuint16_t, svuint16x2_t, + svmop4s_1x2_za32_u16_u16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_u16_u16_3: +** ... +** umop4s za3\.s, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_u16_u16_3, svuint16_t, svuint16x2_t, + svmop4s_1x2_za32_u16_u16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_u16_u16_0: +** ... +** umop4s za0\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_u16_u16_0, svuint16x2_t, svuint16_t, + svmop4s_2x1_za32_u16_u16 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_u16_u16_3: +** ... +** umop4s za3\.s, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_u16_u16_3, svuint16x2_t, svuint16_t, + svmop4s_2x1_za32_u16_u16 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_u16_u16_0: +** ... +** umop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_u16_u16_0, svuint16x2_t, + svmop4s_2x2_za32_u16_u16 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_2x2_za32_u16_u16_3: +** ... +** umop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_u16_u16_3, svuint16x2_t, + svmop4s_2x2_za32_u16_u16 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c new file mode 100644 index 000000000000..7dc4f560ecc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_u8_s8_0: +** ... +** usmop4s za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za32_u8_s8_0, svuint8_t, svint8_t, + svmop4s_1x1_za32_u8_s8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x1_za32_u8_s8_3: +** ... +** usmop4s za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za32_u8_s8_3, svuint8_t, svint8_t, + svmop4s_1x1_za32_u8_s8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_1x2_za32_u8_s8_0: +** ... +** usmop4s za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_u8_s8_0, svuint8_t, svint8x2_t, + svmop4s_1x2_za32_u8_s8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_u8_s8_3: +** ... +** usmop4s za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_u8_s8_3, svuint8_t, svint8x2_t, + svmop4s_1x2_za32_u8_s8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_u8_s8_0: +** ... +** usmop4s za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_u8_s8_0, svuint8x2_t, svint8_t, + svmop4s_2x1_za32_u8_s8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_u8_s8_3: +** ... +** usmop4s za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_u8_s8_3, svuint8x2_t, svint8_t, + svmop4s_2x1_za32_u8_s8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_u8_s8_0: +** ... +** usmop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za32_u8_s8_0, svuint8x2_t, svint8x2_t, + svmop4s_2x2_za32_u8_s8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x2_za32_u8_s8_3: +** ... +** usmop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za32_u8_s8_3, svuint8x2_t, svint8x2_t, + svmop4s_2x2_za32_u8_s8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c new file mode 100644 index 000000000000..a1544833f316 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za32_u8_u8_0: +** ... +** umop4s za0\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_u8_u8_0, svuint8_t, + svmop4s_1x1_za32_u8_u8 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_1x1_za32_u8_u8_3: +** ... +** umop4s za3\.s, z0\.b, z30\.b +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za32_u8_u8_3, svuint8_t, + svmop4s_1x1_za32_u8_u8 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); + +/* +** mop4s_1x2_za32_u8_u8_0: +** ... +** umop4s za0\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_u8_u8_0, svuint8_t, svuint8x2_t, + svmop4s_1x2_za32_u8_u8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_1x2_za32_u8_u8_3: +** ... +** umop4s za3\.s, z0\.b, {z30\.b - z31\.b} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za32_u8_u8_3, svuint8_t, svuint8x2_t, + svmop4s_1x2_za32_u8_u8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x1_za32_u8_u8_0: +** ... +** umop4s za0\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_u8_u8_0, svuint8x2_t, svuint8_t, + svmop4s_2x1_za32_u8_u8 (0, z0, z4), + svmop4s_za32 (0, z0, z4)); + +/* +** mop4s_2x1_za32_u8_u8_3: +** ... +** umop4s za3\.s, {z0\.b - z1\.b}, z30\.b +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za32_u8_u8_3, svuint8x2_t, svuint8_t, + svmop4s_2x1_za32_u8_u8 (3, z0, z4), + svmop4s_za32 (3, z0, z4)); + +/* +** mop4s_2x2_za32_u8_u8_0: +** ... +** umop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_u8_u8_0, svuint8x2_t, + svmop4s_2x2_za32_u8_u8 (0, z0, z1), + svmop4s_za32 (0, z0, z1)); + +/* +** mop4s_2x2_za32_u8_u8_3: +** ... +** umop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za32_u8_u8_3, svuint8x2_t, + svmop4s_2x2_za32_u8_u8 (3, z0, z1), + svmop4s_za32 (3, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c new file mode 100644 index 000000000000..a833eb8159f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-f64f64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za64_f64_f64_0: +** ... +** fmop4s za0\.d, z0\.d, z30\.d +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za64_f64_f64_0, svfloat64_t, + svmop4s_1x1_za64_f64_f64 (0, z0, z1), + svmop4s_za64 (0, z0, z1)); + +/* +** mop4s_1x1_za64_f64_f64_7: +** ... +** fmop4s za7\.d, z0\.d, z30\.d +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za64_f64_f64_7, svfloat64_t, + svmop4s_1x1_za64_f64_f64 (7, z0, z1), + svmop4s_za64 (7, z0, z1)); + +/* +** mop4s_1x2_za64_f64_f64_0: +** ... +** fmop4s za0\.d, z0\.d, {z30\.d - z31\.d} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_f64_f64_0, svfloat64_t, svfloat64x2_t, + svmop4s_1x2_za64_f64_f64 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_1x2_za64_f64_f64_7: +** ... +** fmop4s za7\.d, z0\.d, {z30\.d - z31\.d} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_f64_f64_7, svfloat64_t, svfloat64x2_t, + svmop4s_1x2_za64_f64_f64 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x1_za64_f64_f64_0: +** ... +** fmop4s za0\.d, {z0\.d - z1\.d}, z30\.d +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_f64_f64_0, svfloat64x2_t, svfloat64_t, + svmop4s_2x1_za64_f64_f64 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_2x1_za64_f64_f64_7: +** ... +** fmop4s za7\.d, {z0\.d - z1\.d}, z30\.d +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_f64_f64_7, svfloat64x2_t, svfloat64_t, + svmop4s_2x1_za64_f64_f64 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x2_za64_f64_f64_0: +** ... +** fmop4s za0\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za64_f64_f64_0, svfloat64x2_t, + svmop4s_2x2_za64_f64_f64 (0, z0, z1), + svmop4s_za64 (0, z0, z1)); + +/* +** mop4s_2x2_za64_f64_f64_7: +** ... +** fmop4s za7\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za64_f64_f64_7, svfloat64x2_t, + svmop4s_2x2_za64_f64_f64 (7, z0, z1), + svmop4s_za64 (7, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c new file mode 100644 index 000000000000..3ad801ccbd59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za64_s16_s16_0: +** ... +** smop4s za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za64_s16_s16_0, svint16_t, + svmop4s_1x1_za64_s16_s16 (0, z0, z1), + svmop4s_za64 (0, z0, z1)); + +/* +** mop4s_1x1_za64_s16_s16_7: +** ... +** smop4s za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za64_s16_s16_7, svint16_t, + svmop4s_1x1_za64_s16_s16 (7, z0, z1), + svmop4s_za64 (7, z0, z1)); + +/* +** mop4s_1x2_za64_s16_s16_0: +** ... +** smop4s za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_s16_s16_0, svint16_t, svint16x2_t, + svmop4s_1x2_za64_s16_s16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_1x2_za64_s16_s16_7: +** ... +** smop4s za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_s16_s16_7, svint16_t, svint16x2_t, + svmop4s_1x2_za64_s16_s16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x1_za64_s16_s16_0: +** ... +** smop4s za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_s16_s16_0, svint16x2_t, svint16_t, + svmop4s_2x1_za64_s16_s16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_2x1_za64_s16_s16_7: +** ... +** smop4s za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_s16_s16_7, svint16x2_t, svint16_t, + svmop4s_2x1_za64_s16_s16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x2_za64_s16_s16_0: +** ... +** smop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za64_s16_s16_0, svint16x2_t, + svmop4s_2x2_za64_s16_s16 (0, z0, z1), + svmop4s_za64 (0, z0, z1)); + +/* +** mop4s_2x2_za64_s16_s16_7: +** ... +** smop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za64_s16_s16_7, svint16x2_t, + svmop4s_2x2_za64_s16_s16 (7, z0, z1), + svmop4s_za64 (7, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c new file mode 100644 index 000000000000..269f4fb2b4c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za64_s16_u16_0: +** ... +** sumop4s za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za64_s16_u16_0, svint16_t, svuint16_t, + svmop4s_1x1_za64_s16_u16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_1x1_za64_s16_u16_7: +** ... +** sumop4s za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za64_s16_u16_7, svint16_t, svuint16_t, + svmop4s_1x1_za64_s16_u16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_1x2_za64_s16_u16_0: +** ... +** sumop4s za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_s16_u16_0, svint16_t, svuint16x2_t, + svmop4s_1x2_za64_s16_u16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_1x2_za64_s16_u16_7: +** ... +** sumop4s za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_s16_u16_7, svint16_t, svuint16x2_t, + svmop4s_1x2_za64_s16_u16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x1_za64_s16_u16_0: +** ... +** sumop4s za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_s16_u16_0, svint16x2_t, svuint16_t, + svmop4s_2x1_za64_s16_u16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_2x1_za64_s16_u16_7: +** ... +** sumop4s za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_s16_u16_7, svint16x2_t, svuint16_t, + svmop4s_2x1_za64_s16_u16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x2_za64_s16_u16_0: +** ... +** sumop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za64_s16_u16_0, svint16x2_t, svuint16x2_t, + svmop4s_2x2_za64_s16_u16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_2x2_za64_s16_u16_7: +** ... +** sumop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za64_s16_u16_7, svint16x2_t, svuint16x2_t, + svmop4s_2x2_za64_s16_u16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c new file mode 100644 index 000000000000..21234bd5a2a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za64_u16_s16_0: +** ... +** usmop4s za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za64_u16_s16_0, svuint16_t, svint16_t, + svmop4s_1x1_za64_u16_s16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_1x1_za64_u16_s16_7: +** ... +** usmop4s za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_1x1_za64_u16_s16_7, svuint16_t, svint16_t, + svmop4s_1x1_za64_u16_s16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_1x2_za64_u16_s16_0: +** ... +** usmop4s za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_u16_s16_0, svuint16_t, svint16x2_t, + svmop4s_1x2_za64_u16_s16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_1x2_za64_u16_s16_7: +** ... +** usmop4s za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_u16_s16_7, svuint16_t, svint16x2_t, + svmop4s_1x2_za64_u16_s16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x1_za64_u16_s16_0: +** ... +** usmop4s za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_u16_s16_0, svuint16x2_t, svint16_t, + svmop4s_2x1_za64_u16_s16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_2x1_za64_u16_s16_7: +** ... +** usmop4s za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_u16_s16_7, svuint16x2_t, svint16_t, + svmop4s_2x1_za64_u16_s16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x2_za64_u16_s16_0: +** ... +** usmop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za64_u16_s16_0, svuint16x2_t, svint16x2_t, + svmop4s_2x2_za64_u16_s16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_2x2_za64_u16_s16_7: +** ... +** usmop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_2x2_za64_u16_s16_7, svuint16x2_t, svint16x2_t, + svmop4s_2x2_za64_u16_s16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c new file mode 100644 index 000000000000..1e05bafb5826 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c @@ -0,0 +1,87 @@ +/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +#include <arm_sme.h> +#include "test_sme2_acle.h" + +/* +** mop4s_1x1_za64_u16_u16_0: +** ... +** umop4s za0\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za64_u16_u16_0, svuint16_t, + svmop4s_1x1_za64_u16_u16 (0, z0, z1), + svmop4s_za64 (0, z0, z1)); + +/* +** mop4s_1x1_za64_u16_u16_7: +** ... +** umop4s za7\.d, z0\.h, z30\.h +** ret +*/ +TEST_UNIFORM_ZA (mop4s_1x1_za64_u16_u16_7, svuint16_t, + svmop4s_1x1_za64_u16_u16 (7, z0, z1), + svmop4s_za64 (7, z0, z1)); + +/* +** mop4s_1x2_za64_u16_u16_0: +** ... +** umop4s za0\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_u16_u16_0, svuint16_t, svuint16x2_t, + svmop4s_1x2_za64_u16_u16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_1x2_za64_u16_u16_7: +** ... +** umop4s za7\.d, z0\.h, {z30\.h - z31\.h} +** ret +*/ +TEST_DUAL_ZA (mop4s_1x2_za64_u16_u16_7, svuint16_t, svuint16x2_t, + svmop4s_1x2_za64_u16_u16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x1_za64_u16_u16_0: +** ... +** umop4s za0\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_u16_u16_0, svuint16x2_t, svuint16_t, + svmop4s_2x1_za64_u16_u16 (0, z0, z4), + svmop4s_za64 (0, z0, z4)); + +/* +** mop4s_2x1_za64_u16_u16_7: +** ... +** umop4s za7\.d, {z0\.h - z1\.h}, z30\.h +** ret +*/ +TEST_DUAL_ZA (mop4s_2x1_za64_u16_u16_7, svuint16x2_t, svuint16_t, + svmop4s_2x1_za64_u16_u16 (7, z0, z4), + svmop4s_za64 (7, z0, z4)); + +/* +** mop4s_2x2_za64_u16_u16_0: +** ... +** umop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za64_u16_u16_0, svuint16x2_t, + svmop4s_2x2_za64_u16_u16 (0, z0, z1), + svmop4s_za64 (0, z0, z1)); + +/* +** mop4s_2x2_za64_u16_u16_7: +** ... +** umop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h} +** ret +*/ +TEST_UNIFORM_ZA (mop4s_2x2_za64_u16_u16_7, svuint16x2_t, + svmop4s_2x2_za64_u16_u16 (7, z0, z1), + svmop4s_za64 (7, z0, z1)); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_b16b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_b16b16.c new file mode 100644 index 000000000000..d9a535ba7a71 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_b16b16.c @@ -0,0 +1,79 @@ +// { dg-options "-std=c23 -fsyntax-only" } +// { dg-do compile } + +// svmop4a[_1x1]_za16[_bbf16_bbf16] (only if __ARM_FEATURE_SME_B16B16 != 0) + +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16" +static_assert (__ARM_FEATURE_SME_MOP4 == 1); +static_assert (__ARM_FEATURE_SME_B16B16 == 1); +#include <arm_sme.h> + +void +explicit_ok (svbfloat16_t bf16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_bf16_bf16 (0, bf16, bf16); +} + +void +implicit_ok (svbfloat16_t bf16) __arm_streaming __arm_inout ("za") +{ + svmop4a_za16 (0, bf16, bf16); +} + +void +error_not_streaming (svbfloat16_t bf16) +{ + svmop4a_1x1_za16_bf16_bf16 (0, bf16, bf16); // { dg-error {ACLE function 'svmop4a_1x1_za16_bf16_bf16' can only be called when SME streaming mode is enabled} } + svmop4a_za16 (0, bf16, bf16); // { dg-error {ACLE function 'svmop4a_1x1_za16_bf16_bf16' can only be called when SME streaming mode is enabled} } +} + +void +error_streaming_compatible (svbfloat16_t bf16) __arm_streaming_compatible +{ + svmop4a_1x1_za16_bf16_bf16 (0, bf16, bf16); // { dg-error {ACLE function 'svmop4a_1x1_za16_bf16_bf16' can only be called when SME streaming mode is enabled} } + svmop4a_za16 (0, bf16, bf16); // { dg-error {ACLE function 'svmop4a_1x1_za16_bf16_bf16' can only be called when SME streaming mode is enabled} } +} + +void +error_arg_count_mismatch (svbfloat16_t bf16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_bf16_bf16 (); // { dg-error {too few arguments to function 'svmop4a_1x1_za16_bf16_bf16'; expected 3, have 0} } + svmop4a_za16 (); // { dg-error {too few arguments to function 'svmop4a_za16'} } + + svmop4a_1x1_za16_bf16_bf16 (0, bf16, bf16, 0); // { dg-error {too many arguments to function 'svmop4a_1x1_za16_bf16_bf16'; expected 3, have 4} } + svmop4a_za16 (0, bf16, bf16, 0); // { dg-error {too many arguments to function 'svmop4a_za16'} } +} + +void +error_arg_type_mismatch (svbfloat16_t bf16, svbfloat16x2_t bf16x2, + svbfloat16x4_t bf16x4) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_bf16_bf16 (0, bf16x2, bf16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za16_bf16_bf16'} } + svmop4a_za16 (0, bf16x4, bf16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za16_bf16_bf16'} } +} + +void +error_zt0_not_immediate (uint64_t zt0, + svbfloat16_t bf16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_bf16_bf16 (zt0, bf16, bf16); // { dg-error {argument 1 of 'svmop4a_1x1_za16_bf16_bf16' must be an integer constant expression} } + svmop4a_za16 (zt0, bf16, bf16); // { dg-error {argument 1 of 'svmop4a_za16' must be an integer constant expression} } +} + +void +error_zt0_not_in_range (svbfloat16_t bf16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_bf16_bf16 (-1, bf16, bf16); // { dg-error {passing -1 to argument 1 of 'svmop4a_1x1_za16_bf16_bf16', which expects a value in the range \[0, 1\]} } + svmop4a_za16 (-1, bf16, bf16); // { dg-error {passing -1 to argument 1 of 'svmop4a_za16', which expects a value in the range \[0, 1\]} } + + svmop4a_1x1_za16_bf16_bf16 (2, bf16, bf16); // { dg-error {passing 2 to argument 1 of 'svmop4a_1x1_za16_bf16_bf16', which expects a value in the range \[0, 1\]} } + svmop4a_za16 (2, bf16, bf16); // { dg-error {passing 2 to argument 1 of 'svmop4a_za16', which expects a value in the range \[0, 1\]} } +} + +#pragma GCC target "+nothing,+sve2,+sme2,+sme-mop4" + +void +error_missing_feature (svbfloat16_t bf16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_bf16_bf16 (0, bf16, bf16); // { dg-error {ACLE function 'svmop4a_1x1_za16_bf16_bf16' requires ISA extension 'sme-b16b16'} } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_base.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_base.c new file mode 100644 index 000000000000..5e0629147054 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_base.c @@ -0,0 +1,106 @@ +// { dg-options "-std=c23 -fsyntax-only" } +// { dg-do compile } + +// svmop4a[_1x1]_za32[_f32_f32] +// svmop4a[_1x1]_za32[_f16_f16] +// svmop4a[_1x1]_za32[_bf16_bf16] +// svmop4a[_1x1]_za32[_s16_s16] +// svmop4a[_1x1]_za32[_u16_u16] +// svmop4a[_1x1]_za32[_s8_s8] +// svmop4a[_1x1]_za32[_u8_u8] +// svmop4a[_1x1]_za32[_s8_u8] +// svmop4a[_1x1]_za32[_u8_s8] + +#pragma GCC target "+sve2,+sme-mop4" +static_assert (__ARM_FEATURE_SME_MOP4 == 1); +#include <arm_sme.h> + +void +explicit_ok (svfloat32_t f32, svfloat16_t f16, svbfloat16_t bf16, svint16_t s16, + svuint16_t u16, svint8_t s8, + svuint8_t u8) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_f32_f32 (0, f32, f32); + svmop4a_1x1_za32_f16_f16 (0, f16, f16); + svmop4a_1x1_za32_bf16_bf16 (0, bf16, bf16); + svmop4a_1x1_za32_s16_s16 (0, s16, s16); + svmop4a_1x1_za32_u16_u16 (0, u16, u16); + svmop4a_1x1_za32_s8_s8 (0, s8, s8); + svmop4a_1x1_za32_u8_u8 (0, u8, u8); + svmop4a_1x1_za32_s8_u8 (0, s8, u8); + svmop4a_1x1_za32_u8_s8 (0, u8, s8); +} + +void +implicit_ok (svfloat32_t f32, svfloat16_t f16, svbfloat16_t bf16, svint16_t s16, + svuint16_t u16, svint8_t s8, + svuint8_t u8) __arm_streaming __arm_inout ("za") +{ + svmop4a_za32 (0, f32, f32); + svmop4a_za32 (0, f16, f16); + svmop4a_za32 (0, bf16, bf16); + svmop4a_za32 (0, s16, s16); + svmop4a_za32 (0, u16, u16); + svmop4a_za32 (0, s8, s8); + svmop4a_za32 (0, u8, u8); + svmop4a_za32 (0, s8, u8); + svmop4a_za32 (0, u8, s8); +} + +void +error_not_streaming (svfloat16_t f16) +{ + svmop4a_1x1_za32_f16_f16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za32_f16_f16' can only be called when SME streaming mode is enabled} } + svmop4a_za32 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za32_f16_f16' can only be called when SME streaming mode is enabled} } +} + +void +error_streaming_compatible (svfloat16_t f16) __arm_streaming_compatible +{ + svmop4a_1x1_za32_f16_f16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za32_f16_f16' can only be called when SME streaming mode is enabled} } + svmop4a_za32 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za32_f16_f16' can only be called when SME streaming mode is enabled} } +} + +void +error_arg_count_mismatch (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_f16_f16 (); // { dg-error {too few arguments to function 'svmop4a_1x1_za32_f16_f16'; expected 3, have 0} } + svmop4a_za32 (); // { dg-error {too few arguments to function 'svmop4a_za32'} } + + svmop4a_1x1_za32_f16_f16 (0, f16, f16, 0); // { dg-error {too many arguments to function 'svmop4a_1x1_za32_f16_f16'; expected 3, have 4} } + svmop4a_za32 (0, f16, f16, 0); // { dg-error {too many arguments to function 'svmop4a_za32'} } +} + +void +error_arg_type_mismatch (svfloat16_t f16, svfloat16x2_t f16x2, + svfloat16x4_t f16x4) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_f16_f16 (0, f16x2, f16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za32_f16_f16'} } + svmop4a_za32 (0, f16x4, f16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za32_f16_f16'} } +} + +void +error_zt0_not_immediate (uint64_t zt0, + svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_f16_f16 (zt0, f16, f16); // { dg-error {argument 1 of 'svmop4a_1x1_za32_f16_f16' must be an integer constant expression} } + svmop4a_za32 (zt0, f16, f16); // { dg-error {argument 1 of 'svmop4a_za32' must be an integer constant expression} } +} + +void +error_zt0_not_in_range (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_f16_f16 (-1, f16, f16); // { dg-error {passing -1 to argument 1 of 'svmop4a_1x1_za32_f16_f16', which expects a value in the range \[0, 3\]} } + svmop4a_za32 (-1, f16, f16); // { dg-error {passing -1 to argument 1 of 'svmop4a_za32', which expects a value in the range \[0, 3\]} } + + svmop4a_1x1_za32_f16_f16 (4, f16, f16); // { dg-error {passing 4 to argument 1 of 'svmop4a_1x1_za32_f16_f16', which expects a value in the range \[0, 3\]} } + svmop4a_za32 (4, f16, f16); // { dg-error {passing 4 to argument 1 of 'svmop4a_za32', which expects a value in the range \[0, 3\]} } +} + +#pragma GCC target "+nothing,+sve2,+sme2" + +void +error_missing_feature (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_f16_f16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za32_f16_f16' requires ISA extension 'sme-mop4'} } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f16f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f16f16.c new file mode 100644 index 000000000000..dd5fc855b475 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f16f16.c @@ -0,0 +1,79 @@ +// { dg-options "-std=c23 -fsyntax-only" } +// { dg-do compile } + +// svmop4a[_1x1]_za16[_f16_f16] (only if __ARM_FEATURE_SME_F16F16 != 0) + +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16" +static_assert (__ARM_FEATURE_SME_MOP4 == 1); +static_assert (__ARM_FEATURE_SME_F16F16 == 1); +#include <arm_sme.h> + +void +explicit_ok (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_f16_f16 (0, f16, f16); +} + +void +implicit_ok (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_za16 (0, f16, f16); +} + +void +error_not_streaming (svfloat16_t f16) +{ + svmop4a_1x1_za16_f16_f16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za16_f16_f16' can only be called when SME streaming mode is enabled} } + svmop4a_za16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za16_f16_f16' can only be called when SME streaming mode is enabled} } +} + +void +error_streaming_compatible (svfloat16_t f16) __arm_streaming_compatible +{ + svmop4a_1x1_za16_f16_f16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za16_f16_f16' can only be called when SME streaming mode is enabled} } + svmop4a_za16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za16_f16_f16' can only be called when SME streaming mode is enabled} } +} + +void +error_arg_count_mismatch (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_f16_f16 (); // { dg-error {too few arguments to function 'svmop4a_1x1_za16_f16_f16'; expected 3, have 0} } + svmop4a_za16 (); // { dg-error {too few arguments to function 'svmop4a_za16'} } + + svmop4a_1x1_za16_f16_f16 (0, f16, f16, 0); // { dg-error {too many arguments to function 'svmop4a_1x1_za16_f16_f16'; expected 3, have 4} } + svmop4a_za16 (0, f16, f16, 0); // { dg-error {too many arguments to function 'svmop4a_za16'} } +} + +void +error_arg_type_mismatch (svfloat16_t f16, svfloat16x2_t f16x2, + svfloat16x4_t f16x4) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_f16_f16 (0, f16x2, f16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za16_f16_f16'} } + svmop4a_za16 (0, f16x4, f16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za16_f16_f16'} } +} + +void +error_zt0_not_immediate (uint64_t zt0, + svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_f16_f16 (zt0, f16, f16); // { dg-error {argument 1 of 'svmop4a_1x1_za16_f16_f16' must be an integer constant expression} } + svmop4a_za16 (zt0, f16, f16); // { dg-error {argument 1 of 'svmop4a_za16' must be an integer constant expression} } +} + +void +error_zt0_not_in_range (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_f16_f16 (-1, f16, f16); // { dg-error {passing -1 to argument 1 of 'svmop4a_1x1_za16_f16_f16', which expects a value in the range \[0, 1\]} } + svmop4a_za16 (-1, f16, f16); // { dg-error {passing -1 to argument 1 of 'svmop4a_za16', which expects a value in the range \[0, 1\]} } + + svmop4a_1x1_za16_f16_f16 (2, f16, f16); // { dg-error {passing 2 to argument 1 of 'svmop4a_1x1_za16_f16_f16', which expects a value in the range \[0, 1\]} } + svmop4a_za16 (2, f16, f16); // { dg-error {passing 2 to argument 1 of 'svmop4a_za16', which expects a value in the range \[0, 1\]} } +} + +#pragma GCC target "+nothing,+sve2,+sme2,+sme-mop4" + +void +error_missing_feature (svfloat16_t f16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_f16_f16 (0, f16, f16); // { dg-error {ACLE function 'svmop4a_1x1_za16_f16_f16' requires ISA extension 'sme-f16f16'} } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f64f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f64f64.c new file mode 100644 index 000000000000..9a899f5eaa7b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f64f64.c @@ -0,0 +1,79 @@ +// { dg-options "-std=c23 -fsyntax-only" } +// { dg-do compile } + +// svmop4a[_1x1]_za64[_f64_f64] (only if __ARM_FEATURE_SME_F64F64 != 0) + +#pragma GCC target "+sve2,+sme-mop4,+sme-f64f64" +static_assert (__ARM_FEATURE_SME_MOP4 == 1); +static_assert (__ARM_FEATURE_SME_F64F64 == 1); +#include <arm_sme.h> + +void +explicit_ok (svfloat64_t f64) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_f64_f64 (0, f64, f64); +} + +void +implicit_ok (svfloat64_t f64) __arm_streaming __arm_inout ("za") +{ + svmop4a_za64 (0, f64, f64); +} + +void +error_not_streaming (svfloat64_t f64) +{ + svmop4a_1x1_za64_f64_f64 (0, f64, f64); // { dg-error {ACLE function 'svmop4a_1x1_za64_f64_f64' can only be called when SME streaming mode is enabled} } + svmop4a_za64 (0, f64, f64); // { dg-error {ACLE function 'svmop4a_1x1_za64_f64_f64' can only be called when SME streaming mode is enabled} } +} + +void +error_streaming_compatible (svfloat64_t f64) __arm_streaming_compatible +{ + svmop4a_1x1_za64_f64_f64 (0, f64, f64); // { dg-error {ACLE function 'svmop4a_1x1_za64_f64_f64' can only be called when SME streaming mode is enabled} } + svmop4a_za64 (0, f64, f64); // { dg-error {ACLE function 'svmop4a_1x1_za64_f64_f64' can only be called when SME streaming mode is enabled} } +} + +void +error_arg_count_mismatch (svfloat64_t f64) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_f64_f64 (); // { dg-error {too few arguments to function 'svmop4a_1x1_za64_f64_f64'; expected 3, have 0} } + svmop4a_za64 (); // { dg-error {too few arguments to function 'svmop4a_za64'} } + + svmop4a_1x1_za64_f64_f64 (0, f64, f64, 0); // { dg-error {too many arguments to function 'svmop4a_1x1_za64_f64_f64'; expected 3, have 4} } + svmop4a_za64 (0, f64, f64, 0); // { dg-error {too many arguments to function 'svmop4a_za64'} } +} + +void +error_arg_type_mismatch (svfloat64_t f64, svfloat64x2_t f64x2, + svfloat64x4_t f64x4) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_f64_f64 (0, f64x2, f64); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za64_f64_f64'} } + svmop4a_za64 (0, f64x4, f64); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za64_f64_f64'} } +} + +void +error_zt0_not_immediate (uint64_t zt0, + svfloat64_t f64) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_f64_f64 (zt0, f64, f64); // { dg-error {argument 1 of 'svmop4a_1x1_za64_f64_f64' must be an integer constant expression} } + svmop4a_za64 (zt0, f64, f64); // { dg-error {argument 1 of 'svmop4a_za64' must be an integer constant expression} } +} + +void +error_zt0_not_in_range (svfloat64_t f64) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_f64_f64 (-1, f64, f64); // { dg-error {passing -1 to argument 1 of 'svmop4a_1x1_za64_f64_f64', which expects a value in the range \[0, 7\]} } + svmop4a_za64 (-1, f64, f64); // { dg-error {passing -1 to argument 1 of 'svmop4a_za64', which expects a value in the range \[0, 7\]} } + + svmop4a_1x1_za64_f64_f64 (8, f64, f64); // { dg-error {passing 8 to argument 1 of 'svmop4a_1x1_za64_f64_f64', which expects a value in the range \[0, 7\]} } + svmop4a_za64 (8, f64, f64); // { dg-error {passing 8 to argument 1 of 'svmop4a_za64', which expects a value in the range \[0, 7\]} } +} + +#pragma GCC target "+nothing,+sve2,+sme2,+sme-mop4" + +void +error_missing_feature (svfloat64_t f64) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_f64_f64 (0, f64, f64); // { dg-error {ACLE function 'svmop4a_1x1_za64_f64_f64' requires ISA extension 'sme-f64f64'} } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f8f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f8f16.c new file mode 100644 index 000000000000..56021dc8cd9d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f8f16.c @@ -0,0 +1,84 @@ +// { dg-options "-std=c23 -fsyntax-only" } +// { dg-do compile } + +// svmop4a[_1x1]_za16[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F16 != 0) + +#pragma GCC target "+sve2,+sme-mop4,+sme-f8f16" +static_assert (__ARM_FEATURE_SME_MOP4 == 1); +static_assert (__ARM_FEATURE_SME_F8F16 == 1); +#include <arm_sme.h> + +void +explicit_ok (svmfloat8_t mf8, fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_mf8_mf8_fpm (0, mf8, mf8, fpm); +} + +void +implicit_ok (svmfloat8_t mf8, fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_za16_fpm (0, mf8, mf8, fpm); +} + +void +error_not_streaming (svmfloat8_t mf8, fpm_t fpm) +{ + svmop4a_1x1_za16_mf8_mf8_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za16_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } + svmop4a_za16_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za16_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } +} + +void +error_streaming_compatible (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming_compatible +{ + svmop4a_1x1_za16_mf8_mf8_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za16_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } + svmop4a_za16_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za16_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } +} + +void +error_arg_count_mismatch (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_mf8_mf8_fpm (); // { dg-error {too few arguments to function 'svmop4a_1x1_za16_mf8_mf8_fpm'; expected 4, have 0} } + svmop4a_za16_fpm (); // { dg-error {too few arguments to function 'svmop4a_za16_fpm'} } + + svmop4a_1x1_za16_mf8_mf8_fpm (0, mf8, mf8, fpm, 0); // { dg-error {too many arguments to function 'svmop4a_1x1_za16_mf8_mf8_fpm'; expected 4, have 5} } + svmop4a_za16_fpm (0, mf8, mf8, fpm, 0); // { dg-error {too many arguments to function 'svmop4a_za16_fpm'} } +} + +void +error_arg_type_mismatch (svmfloat8_t mf8, svmfloat8x2_t mf8x2, + svmfloat8x4_t mf8x4, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_mf8_mf8_fpm (0, mf8x2, mf8, fpm); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za16_mf8_mf8_fpm'} } + svmop4a_za16_fpm (0, mf8x4, mf8, fpm); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za16_mf8_mf8_fpm'} } +} + +void +error_zt0_not_immediate (uint64_t zt0, svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_mf8_mf8_fpm (zt0, mf8, mf8, fpm); // { dg-error {argument 1 of 'svmop4a_1x1_za16_mf8_mf8_fpm' must be an integer constant expression} } + svmop4a_za16_fpm (zt0, mf8, mf8, fpm); // { dg-error {argument 1 of 'svmop4a_za16_fpm' must be an integer constant expression} } +} + +void +error_zt0_not_in_range (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_mf8_mf8_fpm (-1, mf8, mf8, fpm); // { dg-error {passing -1 to argument 1 of 'svmop4a_1x1_za16_mf8_mf8_fpm', which expects a value in the range \[0, 1\]} } + svmop4a_za16_fpm (-1, mf8, mf8, fpm); // { dg-error {passing -1 to argument 1 of 'svmop4a_za16_fpm', which expects a value in the range \[0, 1\]} } + + svmop4a_1x1_za16_mf8_mf8_fpm (2, mf8, mf8, fpm); // { dg-error {passing 2 to argument 1 of 'svmop4a_1x1_za16_mf8_mf8_fpm', which expects a value in the range \[0, 1\]} } + svmop4a_za16_fpm (2, mf8, mf8, fpm); // { dg-error {passing 2 to argument 1 of 'svmop4a_za16_fpm', which expects a value in the range \[0, 1\]} } +} + +#pragma GCC target "+nothing,+sve2,+sme2,+sme-mop4" + +void +error_missing_feature (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za16_mf8_mf8_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za16_mf8_mf8_fpm' requires ISA extension 'sme-f8f16'} } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f8f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f8f32.c new file mode 100644 index 000000000000..21c159a61e6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_f8f32.c @@ -0,0 +1,84 @@ +// { dg-options "-std=c23 -fsyntax-only" } +// { dg-do compile } + +// svmop4a[_1x1]_za32[_mf8_mf8]_fpm (only if __ARM_FEATURE_SME_F8F32 != 0) + +#pragma GCC target "+sve2,+sme-mop4,+sme-f8f32" +static_assert (__ARM_FEATURE_SME_MOP4 == 1); +static_assert (__ARM_FEATURE_SME_F8F32 == 1); +#include <arm_sme.h> + +void +explicit_ok (svmfloat8_t mf8, fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_mf8_mf8_fpm (0, mf8, mf8, fpm); +} + +void +implicit_ok (svmfloat8_t mf8, fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_za32_fpm (0, mf8, mf8, fpm); +} + +void +error_not_streaming (svmfloat8_t mf8, fpm_t fpm) +{ + svmop4a_1x1_za32_mf8_mf8_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za32_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } + svmop4a_za32_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za32_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } +} + +void +error_streaming_compatible (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming_compatible +{ + svmop4a_1x1_za32_mf8_mf8_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za32_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } + svmop4a_za32_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za32_mf8_mf8_fpm' can only be called when SME streaming mode is enabled} } +} + +void +error_arg_count_mismatch (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_mf8_mf8_fpm (); // { dg-error {too few arguments to function 'svmop4a_1x1_za32_mf8_mf8_fpm'; expected 4, have 0} } + svmop4a_za32_fpm (); // { dg-error {too few arguments to function 'svmop4a_za32_fpm'} } + + svmop4a_1x1_za32_mf8_mf8_fpm (0, mf8, mf8, fpm, 0); // { dg-error {too many arguments to function 'svmop4a_1x1_za32_mf8_mf8_fpm'; expected 4, have 5} } + svmop4a_za32_fpm (0, mf8, mf8, fpm, 0); // { dg-error {too many arguments to function 'svmop4a_za32_fpm'} } +} + +void +error_arg_type_mismatch (svmfloat8_t mf8, svmfloat8x2_t mf8x2, + svmfloat8x4_t mf8x4, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_mf8_mf8_fpm (0, mf8x2, mf8, fpm); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za32_mf8_mf8_fpm'} } + svmop4a_za32_fpm (0, mf8x4, mf8, fpm); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za32_mf8_mf8_fpm'} } +} + +void +error_zt0_not_immediate (uint64_t zt0, svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_mf8_mf8_fpm (zt0, mf8, mf8, fpm); // { dg-error {argument 1 of 'svmop4a_1x1_za32_mf8_mf8_fpm' must be an integer constant expression} } + svmop4a_za32_fpm (zt0, mf8, mf8, fpm); // { dg-error {argument 1 of 'svmop4a_za32_fpm' must be an integer constant expression} } +} + +void +error_zt0_not_in_range (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_mf8_mf8_fpm (-1, mf8, mf8, fpm); // { dg-error {passing -1 to argument 1 of 'svmop4a_1x1_za32_mf8_mf8_fpm', which expects a value in the range \[0, 3\]} } + svmop4a_za32_fpm (-1, mf8, mf8, fpm); // { dg-error {passing -1 to argument 1 of 'svmop4a_za32_fpm', which expects a value in the range \[0, 3\]} } + + svmop4a_1x1_za32_mf8_mf8_fpm (4, mf8, mf8, fpm); // { dg-error {passing 4 to argument 1 of 'svmop4a_1x1_za32_mf8_mf8_fpm', which expects a value in the range \[0, 3\]} } + svmop4a_za32_fpm (4, mf8, mf8, fpm); // { dg-error {passing 4 to argument 1 of 'svmop4a_za32_fpm', which expects a value in the range \[0, 3\]} } +} + +#pragma GCC target "+nothing,+sve2,+sme2,+sme-mop4" + +void +error_missing_feature (svmfloat8_t mf8, + fpm_t fpm) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za32_mf8_mf8_fpm (0, mf8, mf8, fpm); // { dg-error {ACLE function 'svmop4a_1x1_za32_mf8_mf8_fpm' requires ISA extension 'sme-f8f32'} } +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_i16i64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_i16i64.c new file mode 100644 index 000000000000..ace25ff9a7b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mop4_i16i64.c @@ -0,0 +1,88 @@ +// { dg-options "-std=c23 -fsyntax-only" } +// { dg-do compile } + +// svmop4a[_1x1]_za64[_s16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_u16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_s16_u16] (only if __ARM_FEATURE_SME_I16I64 != 0) +// svmop4a[_1x1]_za64[_u16_s16] (only if __ARM_FEATURE_SME_I16I64 != 0) + +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64" +static_assert (__ARM_FEATURE_SME_MOP4 == 1); +static_assert (__ARM_FEATURE_SME_I16I64 == 1); +#include <arm_sme.h> + +void +explicit_ok (svint16_t s16, svuint16_t u16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_s16_s16 (0, s16, s16); + svmop4a_1x1_za64_u16_u16 (0, u16, u16); + svmop4a_1x1_za64_s16_u16 (0, s16, u16); + svmop4a_1x1_za64_u16_s16 (0, u16, s16); +} + +void +implicit_ok (svint16_t s16, svuint16_t u16) __arm_streaming __arm_inout ("za") +{ + svmop4a_za64 (0, s16, s16); + svmop4a_za64 (0, u16, u16); + svmop4a_za64 (0, s16, u16); + svmop4a_za64 (0, u16, s16); +} + +void +error_not_streaming (svint16_t s16) +{ + svmop4a_1x1_za64_s16_s16 (0, s16, s16); // { dg-error {ACLE function 'svmop4a_1x1_za64_s16_s16' can only be called when SME streaming mode is enabled} } + svmop4a_za64 (0, s16, s16); // { dg-error {ACLE function 'svmop4a_1x1_za64_s16_s16' can only be called when SME streaming mode is enabled} } +} + +void +error_streaming_compatible (svint16_t s16) __arm_streaming_compatible +{ + svmop4a_1x1_za64_s16_s16 (0, s16, s16); // { dg-error {ACLE function 'svmop4a_1x1_za64_s16_s16' can only be called when SME streaming mode is enabled} } + svmop4a_za64 (0, s16, s16); // { dg-error {ACLE function 'svmop4a_1x1_za64_s16_s16' can only be called when SME streaming mode is enabled} } +} + +void +error_arg_count_mismatch (svint16_t s16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_s16_s16 (); // { dg-error {too few arguments to function 'svmop4a_1x1_za64_s16_s16'; expected 3, have 0} } + svmop4a_za64 (); // { dg-error {too few arguments to function 'svmop4a_za64'} } + + svmop4a_1x1_za64_s16_s16 (0, s16, s16, 0); // { dg-error {too many arguments to function 'svmop4a_1x1_za64_s16_s16'; expected 3, have 4} } + svmop4a_za64 (0, s16, s16, 0); // { dg-error {too many arguments to function 'svmop4a_za64'} } +} + +void +error_arg_type_mismatch (svint16_t s16, svint16x2_t s16x2, + svint16x4_t s16x4) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_s16_s16 (0, s16x2, s16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za64_s16_s16'} } + svmop4a_za64 (0, s16x4, s16); // { dg-error {incompatible type for argument 2 of 'svmop4a_1x1_za64_s16_s16'} } +} + +void +error_zt0_not_immediate (uint64_t zt0, + svint16_t s16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_s16_s16 (zt0, s16, s16); // { dg-error {argument 1 of 'svmop4a_1x1_za64_s16_s16' must be an integer constant expression} } + svmop4a_za64 (zt0, s16, s16); // { dg-error {argument 1 of 'svmop4a_za64' must be an integer constant expression} } +} + +void +error_zt0_not_in_range (svint16_t s16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_s16_s16 (-1, s16, s16); // { dg-error {passing -1 to argument 1 of 'svmop4a_1x1_za64_s16_s16', which expects a value in the range \[0, 7\]} } + svmop4a_za64 (-1, s16, s16); // { dg-error {passing -1 to argument 1 of 'svmop4a_za64', which expects a value in the range \[0, 7\]} } + + svmop4a_1x1_za64_s16_s16 (8, s16, s16); // { dg-error {passing 8 to argument 1 of 'svmop4a_1x1_za64_s16_s16', which expects a value in the range \[0, 7\]} } + svmop4a_za64 (8, s16, s16); // { dg-error {passing 8 to argument 1 of 'svmop4a_za64', which expects a value in the range \[0, 7\]} } +} + +#pragma GCC target "+nothing,+sve2,+sme2,+sme-mop4" + +void +error_missing_feature (svint16_t s16) __arm_streaming __arm_inout ("za") +{ + svmop4a_1x1_za64_s16_s16 (0, s16, s16); // { dg-error {ACLE function 'svmop4a_1x1_za64_s16_s16' requires ISA extension 'sme-i16i64'} } +}