[gcc r17-3548] RISC-V: Add test cases for vwmul.vx reg overlap

https://gcc.gnu.org/g:1a92288ed6cf63c5b9e030506aa31c633af2ac14

commit r17-3548-g1a92288ed6cf63c5b9e030506aa31c633af2ac14
Author: Pan Li <[email protected]>
Date:   Thu Aug 20 08:49:16 2026 +0800

    RISC-V: Add test cases for vwmul.vx reg overlap
    
    Add test cases for register group overlap, please
    note it is not overlap as much as possible.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf8.c: New test.
    
    Signed-off-by: Pan Li <[email protected]>

Diff:
---
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m1.c | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m2.c | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m4.c | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmul_vx-i16-mf2.c      | 19 +++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmul_vx-i16-mf4.c      | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m1.c | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m2.c | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m4.c | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmul_vx-i32-mf2.c      | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m1.c  | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m2.c  | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m4.c  | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf2.c | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf4.c | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf8.c | 19 +++++++++++++++++++
 15 files changed, 276 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m1.c
new file mode 100644
index 000000000000..b7b5c960e50c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m1,
+  vint16m1_t,
+  vint32m2_t,
+  int16_t,
+  __riscv_vle16_v_i16m1,
+  __riscv_vwmul_vx_i32m2,
+  __riscv_vse32_v_i32m2,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v1,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v2,v3,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m2.c
new file mode 100644
index 000000000000..8e5eebd4d21a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m2,
+  vint16m2_t,
+  vint32m4_t,
+  int16_t,
+  __riscv_vle16_v_i16m2,
+  __riscv_vwmul_vx_i32m4,
+  __riscv_vse32_v_i32m4,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v2,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v4,v6,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m4.c
new file mode 100644
index 000000000000..e5433827ca08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-m4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m4,
+  vint16m4_t,
+  vint32m8_t,
+  int16_t,
+  __riscv_vle16_v_i16m4,
+  __riscv_vwmul_vx_i32m8,
+  __riscv_vse32_v_i32m8,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v4,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v8,v12,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf2.c
new file mode 100644
index 000000000000..598d50aa1172
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m1,
+  vint16mf2_t,
+  vint32m1_t,
+  int16_t,
+  __riscv_vle16_v_i16mf2,
+  __riscv_vwmul_vx_i32m1,
+  __riscv_vse32_v_i32m1,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf4.c
new file mode 100644
index 000000000000..83e71e402987
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i16-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m1,
+  vint16mf4_t,
+  vint32mf2_t,
+  int16_t,
+  __riscv_vle16_v_i16mf4,
+  __riscv_vwmul_vx_i32mf2,
+  __riscv_vse32_v_i32mf2,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m1.c
new file mode 100644
index 000000000000..ab1c4c9d9050
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m1,
+  vint32m1_t,
+  vint64m2_t,
+  int32_t,
+  __riscv_vle32_v_i32m1,
+  __riscv_vwmul_vx_i64m2,
+  __riscv_vse64_v_i64m2,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v1,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v2,v3,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m2.c
new file mode 100644
index 000000000000..1d9009b15dae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m2,
+  vint32m2_t,
+  vint64m4_t,
+  int32_t,
+  __riscv_vle32_v_i32m2,
+  __riscv_vwmul_vx_i64m4,
+  __riscv_vse64_v_i64m4,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v2,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v4,v6,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m4.c
new file mode 100644
index 000000000000..2bfabc7c5112
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-m4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m4,
+  vint32m4_t,
+  vint64m8_t,
+  int32_t,
+  __riscv_vle32_v_i32m4,
+  __riscv_vwmul_vx_i64m8,
+  __riscv_vse64_v_i64m8,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v4,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v8,v12,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-mf2.c
new file mode 100644
index 000000000000..63eb5a63bb70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i32-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m1,
+  vint32mf2_t,
+  vint64m1_t,
+  int32_t,
+  __riscv_vle32_v_i32mf2,
+  __riscv_vwmul_vx_i64m1,
+  __riscv_vse64_v_i64m1,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m1.c
new file mode 100644
index 000000000000..42022fa86294
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vint8m1_t,
+  vint16m2_t,
+  int8_t,
+  __riscv_vle8_v_i8m1,
+  __riscv_vwmul_vx_i16m2,
+  __riscv_vse16_v_i16m2,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v1,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v2,v3,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m2.c
new file mode 100644
index 000000000000..bfb179746b9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m2,
+  vint8m2_t,
+  vint16m4_t,
+  int8_t,
+  __riscv_vle8_v_i8m2,
+  __riscv_vwmul_vx_i16m4,
+  __riscv_vse16_v_i16m4,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v2,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v4,v6,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m4.c
new file mode 100644
index 000000000000..f697680fdb58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-m4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m4,
+  vint8m4_t,
+  vint16m8_t,
+  int8_t,
+  __riscv_vle8_v_i8m4,
+  __riscv_vwmul_vx_i16m8,
+  __riscv_vse16_v_i16m8,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v0,v4,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vx\s+v8,v12,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf2.c
new file mode 100644
index 000000000000..0d1bd1539914
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vint8mf2_t,
+  vint16m1_t,
+  int8_t,
+  __riscv_vle8_v_i8mf2,
+  __riscv_vwmul_vx_i16m1,
+  __riscv_vse16_v_i16m1,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf4.c
new file mode 100644
index 000000000000..1c73ce762875
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vint8mf4_t,
+  vint16mf2_t,
+  int8_t,
+  __riscv_vle8_v_i8mf4,
+  __riscv_vwmul_vx_i16mf2,
+  __riscv_vse16_v_i16mf2,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf8.c
new file mode 100644
index 000000000000..6a431f93fc55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vx-i8-mf8.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vint8mf8_t,
+  vint16mf4_t,
+  int8_t,
+  __riscv_vle8_v_i8mf8,
+  __riscv_vwmul_vx_i16mf4,
+  __riscv_vse16_v_i16mf4,
+  vwmul_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vx\s+(v[0-9]+),\1,} } } */