[gcc r17-3549] RISC-V: Add test cases for vwmulu.vx reg overlap

https://gcc.gnu.org/g:531ee609ca37faa59dd11df4658902d2202c0b66

commit r17-3549-g531ee609ca37faa59dd11df4658902d2202c0b66
Author: Pan Li <[email protected]>
Date:   Thu Aug 20 08:49:16 2026 +0800

    RISC-V: Add test cases for vwmulu.vx reg overlap
    
    Add test cases for register group overlap, please
    note it is not overlap as much as possible.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf8.c: New test.
    
    Signed-off-by: Pan Li <[email protected]>

Diff:
---
 .../rvv/autovec/group_overlap/vwmulu_vx-u16-m1.c      | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u16-m2.c      | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u16-m4.c      | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u16-mf2.c     | 19 +++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u16-mf4.c     | 19 +++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u32-m1.c      | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u32-m2.c      | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u32-m4.c      | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u32-mf2.c     | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m1.c | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m2.c | 18 ++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m4.c | 18 ++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u8-mf2.c      | 19 +++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u8-mf4.c      | 19 +++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmulu_vx-u8-mf8.c      | 19 +++++++++++++++++++
 15 files changed, 276 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m1.c
new file mode 100644
index 000000000000..2a5e5616aeb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m1,
+  vuint16m1_t,
+  vuint32m2_t,
+  uint16_t,
+  __riscv_vle16_v_u16m1,
+  __riscv_vwmulu_vx_u32m2,
+  __riscv_vse32_v_u32m2,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v1,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v2,v3,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m2.c
new file mode 100644
index 000000000000..7a7a0cb615c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m2,
+  vuint16m2_t,
+  vuint32m4_t,
+  uint16_t,
+  __riscv_vle16_v_u16m2,
+  __riscv_vwmulu_vx_u32m4,
+  __riscv_vse32_v_u32m4,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v2,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v4,v6,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m4.c
new file mode 100644
index 000000000000..6bce37e33077
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-m4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m4,
+  vuint16m4_t,
+  vuint32m8_t,
+  uint16_t,
+  __riscv_vle16_v_u16m4,
+  __riscv_vwmulu_vx_u32m8,
+  __riscv_vse32_v_u32m8,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v4,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v8,v12,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf2.c
new file mode 100644
index 000000000000..a961145c0efb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf2_t,
+  vuint32m1_t,
+  uint16_t,
+  __riscv_vle16_v_u16mf2,
+  __riscv_vwmulu_vx_u32m1,
+  __riscv_vse32_v_u32m1,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf4.c
new file mode 100644
index 000000000000..630b3a4d986a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u16-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf4_t,
+  vuint32mf2_t,
+  uint16_t,
+  __riscv_vle16_v_u16mf4,
+  __riscv_vwmulu_vx_u32mf2,
+  __riscv_vse32_v_u32mf2,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m1.c
new file mode 100644
index 000000000000..3598d5f52dd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m1,
+  vuint32m1_t,
+  vuint64m2_t,
+  uint32_t,
+  __riscv_vle32_v_u32m1,
+  __riscv_vwmulu_vx_u64m2,
+  __riscv_vse64_v_u64m2,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v1,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v2,v3,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m2.c
new file mode 100644
index 000000000000..e1fd486d516d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m2,
+  vuint32m2_t,
+  vuint64m4_t,
+  uint32_t,
+  __riscv_vle32_v_u32m2,
+  __riscv_vwmulu_vx_u64m4,
+  __riscv_vse64_v_u64m4,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v2,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v4,v6,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m4.c
new file mode 100644
index 000000000000..1ea0d11c006c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-m4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m4,
+  vuint32m4_t,
+  vuint64m8_t,
+  uint32_t,
+  __riscv_vle32_v_u32m4,
+  __riscv_vwmulu_vx_u64m8,
+  __riscv_vse64_v_u64m8,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v4,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v8,v12,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-mf2.c
new file mode 100644
index 000000000000..3430d888fbb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u32-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e32m1,
+  vuint32mf2_t,
+  vuint64m1_t,
+  uint32_t,
+  __riscv_vle32_v_u32mf2,
+  __riscv_vwmulu_vx_u64m1,
+  __riscv_vse64_v_u64m1,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m1.c
new file mode 100644
index 000000000000..2ffbe4a41fa7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vuint8m1_t,
+  vuint16m2_t,
+  uint8_t,
+  __riscv_vle8_v_u8m1,
+  __riscv_vwmulu_vx_u16m2,
+  __riscv_vse16_v_u16m2,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v1,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v2,v3,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m2.c
new file mode 100644
index 000000000000..9d9b80a74983
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m2,
+  vuint8m2_t,
+  vuint16m4_t,
+  uint8_t,
+  __riscv_vle8_v_u8m2,
+  __riscv_vwmulu_vx_u16m4,
+  __riscv_vse16_v_u16m4,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v2,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v4,v6,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m4.c
new file mode 100644
index 000000000000..1b828f90e60d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-m4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m4,
+  vuint8m4_t,
+  vuint16m8_t,
+  uint8_t,
+  __riscv_vle8_v_u8m4,
+  __riscv_vwmulu_vx_u16m8,
+  __riscv_vse16_v_u16m8,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v0,v4,} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vx\s+v8,v12,} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf2.c
new file mode 100644
index 000000000000..26d25d83be46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf2_t,
+  vuint16m1_t,
+  uint8_t,
+  __riscv_vle8_v_u8mf2,
+  __riscv_vwmulu_vx_u16m1,
+  __riscv_vse16_v_u16m1,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf4.c
new file mode 100644
index 000000000000..2b927a611820
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf4_t,
+  vuint16mf2_t,
+  uint8_t,
+  __riscv_vle8_v_u8mf4,
+  __riscv_vwmulu_vx_u16mf2,
+  __riscv_vse16_v_u16mf2,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vx\s+(v[0-9]+),\1,} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf8.c
new file mode 100644
index 000000000000..aca68e59c80b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vx-u8-mf8.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_3(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf8_t,
+  vuint16mf4_t,
+  uint8_t,
+  __riscv_vle8_v_u8mf8,
+  __riscv_vwmulu_vx_u16mf4,
+  __riscv_vse16_v_u16mf4,
+  vwmulu_vx,
+  LOOP_DUAL_WIDEN_BINARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap the source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vx\s+(v[0-9]+),\1,} } } */