Re: failing to get the same binary with -masm=intel /-masm=att even with -Wa,-Os

Hello LIU Hao,

---------- P=C5=AFvodn=C3=AD e=E2=80=91mail ----------
Od: LIU Hao <[email protected]>
Komu: Zdenek Sojka <[email protected]>, [email protected]
Datum: 27. 5. 2026 10:19:33
P=C5=99edm=C4=9Bt: Re: failing to get the same binary with -masm=3Dintel/-=
masm=3Datt even 
with -Wa,-Os
"=E5=9C=A8 2026-5-27 01:52, Zdenek Sojka via Gcc-help =E5=86=99=E9=81=93: =

> which then GNU AS encodes with the SIB byte, making it longer, even at -=
Os

> 
> Is this: 
> 1) gcc issue 
> 2) binutils/as issue 
> 3) my issue 
> ? 

It's a missed optimization in GCC. Does the attached patch work for you? =


BTW, LEA index+disp32 without base (LEA_I_D32) has a latency of two cycles=
 
on Intel E-cores, while LEA 
base+disp32 without index (LEA_B_D32) has a latency of only one cycle: 
https://uops.info/table.html 



diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc 
index 660a921e28f9..1252002a49c3 100644 
--- a/gcc/config/i386/i386.cc 
+++ b/gcc/config/i386/i386.cc 
@@ -11510,6 +11510,10 @@ ix86_decompose_address (rtx addr, struct ix86_
address *out) 
if (!base && !disp && index && scale !=3D 1) 
disp =3D const0_rtx; 

+ /* Special case: rewrite index*1+disp into base+disp. */ 
+ if (!base && index && scale =3D=3D 1) 
+ base =3D index, base_reg =3D index_reg, index =3D index_reg =3D NULL_RTX=
; 
+ 
out->base =3D base; 
out->index =3D index; 
out->disp =3D disp; 


"""






thank you for the quick reply




I can confirm your patch fixes that particular testcase




no further testing done




Best regards,
Zdenek