[PATCH v2 2/2] arm: Thumb2 reg preferencing for vfp variant of movsi [PR124043]
Richard Earnshaw via Sourceware Forge <[email protected]>
| Newsgroups | gmane.comp.gcc.patches |
|---|---|
| Message-ID | <bmm.hkwtqyput0.gcc.gcc.rearnsha.208.2.2@forge-stage.sourceware.org> |
From: Richard Earnshaw <[email protected]> This pattern currently masks a lot of alternatives from register preferencing, but this can cause the register allocator to prefer to spill and reload from the stack when transferring values between core and VFP registers. (This is probably exacerbated by LRA also chosing to disparage such alternatives when doing final register selection.) This patch is not a complete rework of the preferences, but does try to bring the alternatives closer to the way we handle registers when compiling in arm mode (A32). This pattern needs reworking - it probably hasn't been looked at properly since we moved to LRA. gcc/ChangeLog: PR target/124043 * config/arm/vfp.md (thumb2_movsi_vfp): Don't hide the t->r alternative from register preferencing. gcc/testsuite/ChangeLog: PR target/124043 * gcc.target/arm/crypto-vsha1cq_u32.c: Remove xfail on vdup. * gcc.target/arm/crypto-vsha1h_u32.c: Likewise. * gcc.target/arm/crypto-vsha1mq_u32.c: Likewise. * gcc.target/arm/crypto-vsha1pq_u32.c: Likewise. --- gcc/config/arm/vfp.md | 8 ++++---- gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c | 2 +- gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c | 2 +- gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c | 2 +- gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index dd9f0c8b6296..3b353d52f5a9 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -276,10 +276,10 @@ ;; is chosen with length 2 when the instruction is predicated for ;; arm_restrict_it. (define_insn "*thumb2_movsi_vfp" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l,*hk,m,*m,*t,\ - r,*t,*t,*Uv, Up, r,Uf,r") - (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk,r,*t,\ - *t,*UvTu,*t, r, Up,r,Uf"))] + [(set (match_operand:SI 0 "nonimmediate_operand" + "=rk,r,l, r,r,l, *hk,m,*m, *t,r,*t,*t, *Uv,Up,r, Uf,r") + (match_operand:SI 1 "general_operand" + "rk, I,Py,K,j,mi,*mi,l,*hk,r, t,*t,*UvTu,*t, r, Up,r, Uf"))] "TARGET_THUMB2 && TARGET_VFP_BASE && ( s_register_operand (operands[0], SImode) || s_register_operand (operands[1], SImode))" diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c index 61c2ee9468c0..1e25c2d3d2c4 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c @@ -31,4 +31,4 @@ uint32_t foo (void) TEST_SHA1C_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1c.32\tq[0-9]+, q[0-9]+} 5 } } */ -/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ +/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c index a4e9a48698c3..71f939103442 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c @@ -27,4 +27,4 @@ uint32_t foo (void) TEST_SHA1H_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1h.32\tq[0-9]+, q[0-9]+} 5 } } */ -/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ +/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c index d1f30d647e36..6929c4ceeb93 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c @@ -31,4 +31,4 @@ uint32_t foo (void) TEST_SHA1M_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1m.32\tq[0-9]+, q[0-9]+} 5 } } */ -/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ +/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c index 43425f3d5ecf..2ef42152853c 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c @@ -31,4 +31,4 @@ uint32_t foo (void) TEST_SHA1P_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1p.32\tq[0-9]+, q[0-9]+} 5 } } */ -/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ +/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */ -- 2.54.0