Re: [PATCH v2 1/3] arm64/sve: Fix missing SVE/FPSIMD endianness conversions

On Wed, Jun 12, 2019 at 05:00:32PM +0100, Dave Martin wrote:
> The in-memory representation of SVE and FPSIMD registers is
> different: the FPSIMD V-registers are stored as single 128-bit
> host-endian values, whereas SVE registers are stored in an
> endianness-invariant byte order.
> 
> This means that the two representations differ when running on a
> big-endian host.  But we blindly copy data from one representation
> to another when converting between the two, resulting in the
> register contents being unintentionally byteswapped in certain
> situations.  Currently this can be triggered by the first SVE
> instruction after a syscall, for example (though the potential
> trigger points may vary in future).
> 
> So, fix the conversion functions fpsimd_to_sve(), sve_to_fpsimd()
> and sve_sync_from_fpsimd_zeropad() to swab where appropriate.
> 
> There is no common swahl128() or swab128() that we could use here.
> Maybe it would be worth making this generic, but for now add a
> simple local hack.
> 
> Since the byte order differences are exposed in ABI, also clarify
> the docuentation.
> 
> Fixes: bc0ee4760364 ("arm64/sve: Core task context handling")
> Fixes: 8cd969d28fd2 ("arm64/sve: Signal handling support")
> Fixes: 43d4da2c45b2 ("arm64/sve: ptrace and ELF coredump support")
> Signed-off-by: Dave Martin <[email protected]>

Thanks, Dave. I've picked this one up and pushed it out to our fixes branch
for 5.2. I assume Catalin will take the other two for 5.3. It's probably
worth proposing some generic 128-bit swab functions too, in case there's any
interest (in which case we could drop our local implementation later on).

Cheers,

Will