Re: Question about YMM register availability in x86 CPUs
Guinevere Larsen via Gdb <[email protected]>
| Newsgroups | gmane.comp.gdb.devel |
|---|---|
| Message-ID | <[email protected]> |
On 6/13/24 10:19 AM, Willgerodt, Felix wrote: >> -----Original Message----- >> From: Gdb <[email protected]> On Behalf >> Of Guinevere Larsen via Gdb >> Sent: Mittwoch, 12. Juni 2024 22:31 >> To: [email protected] >> Subject: Question about YMM register availability in x86 CPUs >> >> Hello gdb list! >> >> TL;DR: Is it reasonable to assume that all x86 CPUs that have AVX >> capabilities will have both XMM and YMM registers? >> > Hi Guinivere, > > The Intel Software Development Manual tells you about AVX > in Volume 1, Chapter 14.1.1: > > "Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7 > in operating modes that are 32-bit or less, YMM0-YMM15 in 64-bit mode). > The lower 128-bits of the YMM registers are aliased to the respective 128-bit > XMM registers" > > In chapter 14.6.1 it tells you what AVX2 added. It is just extending old > instructions to 256 bit and adding new ones. No new register space. > > So I think yes it is reasonable to assume that. > Hi Felix, Thank you for confirming this for me! I'll keep this in mind for future AVX recording development. -- Cheers, Guinevere Larsen She/Her/Hers