parameter case sensitivity

Hi there.

in the course of moving models to verilog, i have hunted down a parameter issue
demonstrated in the following example. consider the input

===
verilog

parameter ONE=1
parameter two=ONE+1
resistor #(two) r(1,2)

list

spice
.print op r(r)
.op
.options noinsensitive
.op
.end
===.

gnucap says
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resistor #(.r(two)) r (.p(1),.n(2));
parameter two not specified, using default
parameter two value is "NOT_INPUT"
parameter two not specified, using default
#           r(r)      
r: short circuit
parameter two not specified, using default
parameter two value is "NOT_INPUT"
parameter two not specified, using default
open circuit: internal node 2
 27.        10.u      
#           r(r)      
 27.        2.        

the behaviour i would expect in "insensitive" mode (which is enabled by the
"spice" command here), is that *more* things (match and there might be
ambiguities).

but currently, *less* things match, such as ONE, or two, because of some
implementation detail. with this you can create a circuit that won't work in
either insensitive nor sensitive mode.

is this worth a fix? or would anybody else consider this a bug?

cheers
felix