Re: sym to verilog-ams

On Tue, Apr 05, 2022 at 12:24:11PM +0200, [email protected] wrote:
> So, what is really the goal (for both sym and sch files) ?
> Is it:

Hey Karl.

This is a good question.

> Is it:
> A, "diff orig_file round_trip_file | wc -c" == 0
> B, sort files by some program and there will be no diffs
> C, converting files to jpg's and they they don't show any differences
> D, the netlists produced with alt. orig/round_trip produces no diff
> E, something else

A C D?. Perhaps A is unrealistic. I do not understand B. E is optional.

> For choise A, one could just include the whole orig_file in the verilog
> file as a comment or something.

Not if you use the list command as suggested. It will print comments as
comments. The real point here (as you have noticed) is to capture the
data of the schematic/symbol including the semantics and represent it in
a neutral object oriented data structure.

You have also noticed that many implementations are based on text
processing like substitution, matching, mangling. Gnucap processes
objects and relations between them, not text.

> For C, there is lepton-schdiff/schdiff.

I like the idea. Are we there yet? When you try, you will find
non-cosmetical issues with nets that need to be addressed.

> About D, the unnamed nets might have different numberings.
> 
> >From what I understand from 
>  https://archive.fosdem.org/2016/schedule/event/eda_data_interchange/
> is that A is not required but D is.

(NB: Such a netlist is created from a schematic by dropping the
positions, the drawings and by grouping the nodes by connectivity --
some call it "spice netlist".)

Yes, D is essential. Two schematics are equivalent if any deterministic
numerical or structural processing produces the same result, and we want
that. If net or node names are non-deterministic in the gEDA netlister,
that would be an exception, we can't address. It is a good test
nevertheless.

I think that a netlist created from a gEDA schematic should be identical
to a netlist created from the corresponding verilog-schematic, if only
Gnucap is used for the steps involved. Note that "netlisting" is not
currently implemented in gnucap-geda, but in Modular Qucs
(experimental).

thanks
felix