Re: sym to verilog-ams

Karl:
> Al Davis:
> > On Sun,  3 Apr 2022 13:14:57 +0200 (CEST)
> > [email protected] wrote:
> > > Can one have mult. identical modules or must a converter output
> > > just one ?
> > 
> > Officially, yes, but you need to provide some way to select which one
> > you want.  This is commonly done to implement things like "binning" and
> > the "level" parameter.
> > 
> > One way to select is `ifdef .  I won't discuss this one further because
> > it is familiar to everyone.
> ...
> 
> I think I prefer the `ifdef version since that would work out of the
> box.

By second thought, the same thing is needed for sch files also.

Regards,
/Karl Hammar