september snapshots

Dear all,

September snapshots for Gnucap [0] and gnucap-modelgen-verilog [1] are
out. Gnucap has seen a couple of minor bugfixes, plus a tweaked short
circuit handler in the resistor plugin. The model generator
implementation has progressed significantly.

The framework for generic constant folding, (numerical) dependency
tracking and dead code elimination has been reworked. A bunch of simple
optimisations have been added in the process, and the interface for
function, filter and task plugins has been streamlined.

A few bugs have been fixed that had affected the numerical stability of
nontrivial semiconductor models and perhaps others. Some usability
improvements have been implemented, the generated code only uses
headers from the Gnucap installation. The preprocessor now supports
`elif and `pragma; The formatting of warnings and error messages has
been improved.

The discipline header has been swapped for the one from ADMS, and so we
no longer depend on copyrighted material. It's up to the users to obtain
their favourite custom versions, and these should generally work as
expected (by means of the search path logic, a discipline header next to
the model file takes precedence over the shipped version).

See the respective NEWS and README files for further details.

Best wishes
felix

[0] https://git.savannah.gnu.org/cgit/gnucap.git/tag/?h=dev-20230930
[1] http://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/tag/?h=20230930-dev