November snapshots

Dear all,

November snapshots for Gnucap [0] and Modelgen-Verilog [1] are ready.

The logic devices in Gnucap have become plugins and permit instantiation
from any language. In particular, the use in Verilog netlists no longer
requires SPICE .subckt wrappers. Their port names and order now agrees
with those defined for built-in primitives in Section 7.8.5.1 of the
Verilog-AMS LRM.

In Modelgen-Verilog, dependency tracking for variables has been
revisited and extended to block level. More elaborate code generation
has enabled smaller device footprints, faster compilation times and
better run-time performance. For example, unused derivatives are no
longer stored and internal nodes are no longer allocated in basic
situations where they are not needed.

This work on Gnucap is funded through the NGI Assure Fund [2], a fund
established by NLnet [3] with financial support from the European
Commission's Next Generation Internet [4] program. Learn more at the
NLnet project page [5].

Best wishes
Felix

[0] https://git.savannah.gnu.org/cgit/gnucap.git/tag/?h=dev-20231130
[1] https://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/tag/?h=20231130-dev
[2] https://nlnet.nl/assure
[3] https://nlnet.nl
[4] https://ngi.eu
[5] https://nlnet.nl/project/Gnucap-VerilogAMS