Verilog syntax (Was: parameter usage in simulation)

On Mon, Apr 20, 2020 at 9:05 AM al davis <[email protected]> wrote:
>
> On Mon, 20 Apr 2020 08:43:55 +0200
> patrick <[email protected]> wrote:
> > module m(1,2);
> >        ^ ? need 4 more nodes
> >
> ...............
> > Surely I am missing some things... anyway thanks for your help.
> >
>
>
> I think it's in spice mode .. expecting spice syntax.
> In spice syntax, a line beginning with 'm' is a mosfet instance.
>
> Commands in spice mode begin with dot, so try ".verilog" to switch to
> verilog mode.
>
>
Thanks Al! Ok, I confirm it looks better with a .verilog at the start.
Also had a quick look at the wiki now:
http://gnucap.org/dokuwiki/doku.php/gnucap:manual:languages:verilog

But trying to run a simple sweep on the Resistor gives:

.verilog

param w=2

module m(1,2);
   resistor #(.r(w*5)) r(1,2);
endmodule

m #(.w(w)) m1(0, 1);

// sweep dc voltage
vin  1  0  dc 3

.dc vin 0 5 0.2


default plugins: cmake-2 2017.10.18

param w=2
^ ? p: no match
m #(.w(w)) m1(0, 1);
                 ^ ? m: 1); has no value?
// sweep dc voltage
^ ? /: no match
vin  1  0  dc 3