Re: Verilog syntax (Was: parameter usage in simulation)

On Mon, Apr 20, 2020 at 12:29:34PM +0200, patrick wrote:
> But trying to run a simple sweep on the Resistor gives:
> 
> .verilog

I suspect that you are running gnucap with the -b flag. this switches on
spice mode, and in spice mode, the first line is the title (effectively
ignored).

try to drop the -b, and put "verilog", without the dot, into the first
line.

cheers
felix