Will Superposition of error flags desynchronize a active-transmitter passive-receiver bus??

Imagine the following situation:

You have a bus with two nodes:
node 1 = transmitter, active-error-node
node 2 = receiver, passive-error-node

Now an error happens at node 1. As it is a active node, it will transmit 6 dominant bits, but... lets suppose that the third bit generate an error in the node2.

The ISO 11898-1:2015, in the page 35 says:

"""""""""""""""""""""""""""""""""""""""
Passive error flags initiated by receivers shall not be able to prevail over any activity on the bus. 
Therefore, error-passive receivers shall always wait for 6 subsequent equal bits after detecting an error condition.
The passive error flag is complete when these 6 equals bits have been detected.
"""""""""""""""""""""""""""""""""""""""

So, from node2's view, it will have to wait 3 (6 total - past 3) dominant bits + 6 recessive bits to follow the rule "6 equal subsequent bits". At the end, node2 can enter in the "error delimiter".
However, from the node1's view, it is remaining only 3 bits to enter in the "error delimiter".

Isn't it happening desynchrony here?

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