RE: Will Superposition of error flags desynchronize a active-transmitter passive-receiver bus??

Hi,
Think back to why a node might be error passive.  Like why is that =
feature even there? =20

A node with a defective bus interface may interpret a large number of  =
transmissions as having errors even though the bus itself is completely =
healthy.  So as the error counter increases they reach that error =
passive state where they internally recognize an error but are no longer =
able to assert the error flag sequence of 6 dominant bits on the bus.  =
Forget about the passive side of the error flag for a moment.

In your example what causes Node 1 to actually generate the error flag?  =
Unless it's at the end of the message with a CRC error a missing stuff =
bit is really the only possibility.  Node 2 has already seen 3 dominant =
bits which implies Node 1 has seen that too.  If it's a missing stuff =
bit then there must have already been at least 3 more dominant bits so =
Node 2 has already a complete error flag. =20

So perhaps, to help us understand your scenario, create two lines of 1's =
and 0's as seen by each of the nodes and place an X where the error =
happens in Node 1 that causes it to issue the error flag.    Show us the =
bit stream for each node that results in your scenario.

Like
Node 2 =3D 01001110000x000...
Node 1 =3D 010011100001000...

I'm wondering if you can even create that scenario that you describe.  =
Remember, if node 2 is somehow badly damaged then it will not ACK the =
message if it thinks there's an error nor can it assert an error flag.  =
That now results in the single node on a bus scenario where node 1 =
repeats forever the message waiting or an ACK or an error flag.

John Dammeyer


> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On
> Behalf Of Christiano SA
> Sent: August-20-18 12:02 PM
> To: [email protected]; [email protected]
> Subject: [CANLIST] Will Superposition of error flags desynchronize a =
active-
> transmitter passive-receiver bus??
>=20
> Imagine the following situation:
>=20
> You have a bus with two nodes:
> node 1 =3D transmitter, active-error-node
> node 2 =3D receiver, passive-error-node
>=20
> Now an error happens at node 1. As it is a active node, it will =
transmit 6
> dominant bits, but... lets suppose that the third bit generate an =
error in the
> node2.
>=20
> The ISO 11898-1:2015, in the page 35 says:
>=20
> """""""""""""""""""""""""""""""""""""""
> Passive error flags initiated by receivers shall not be able to =
prevail over any
> activity on the bus.
> Therefore, error-passive receivers shall always wait for 6 subsequent =
equal
> bits after detecting an error condition.
> The passive error flag is complete when these 6 equals bits have been
> detected.
> """""""""""""""""""""""""""""""""""""""
>=20
> So, from node2's view, it will have to wait 3 (6 total - past 3) =
dominant bits +
> 6 recessive bits to follow the rule "6 equal subsequent bits". At the =
end,
> node2 can enter in the "error delimiter".
> However, from the node1's view, it is remaining only 3 bits to enter =
in the
> "error delimiter".
>=20
> Isn't it happening desynchrony here?
>=20
> This question is being sended to 2 mailing lists:
> Canlist
> Opengarage group
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