Re: [OpenGarages] Will Superposition of error flags desynchronize a active-transmitter passive-receiver bus??

Conventions:
_ = 0 = dominant bit
- = 1 = recessive bit

Imagine the signal:
______-----------

That is, 6 dominant bits + 11 recessive bits.

If my previous interpretation of ISO was correct (I think that it wasn't), so:

Node1 will interpret it as follow:
______-----------
=
error flag (6 dominant bits) + 
error delimiter (8 recessive bits) +
intermission (3 recessive bits)

Now Node1 thinks that bus is idle and if Node1 has information to transmit, it will send a SOF.

However, 
Node2 will interpret the same signal as follow:
______-----------
=
error flag (6 dominant bits) + 
6 equal recessive bits +
error delimiter ( it has 8 recessive bits but the signal presents only 5 of them)

When Node1 thinks that it can send a SOF, Node2 thinks that it is inside the error delimiter.

--

The correct interpretation probably is to think the "6 subsequent bits", as the ISO says, may have its left edge before of the detection of error condition.
Such interpretation works very well with all cases that I have tested. 

Following such interpretation and applying to previous example, when Node2 detect a error condition, it has only 3 bits additional in order to complete 6 subsequent equal bits and the two nodes would be synchronized.


> Sent: Monday, August 20, 2018 at 4:55 PM
> From: "Collin Kidder" <[email protected]>
> To: [email protected]
> Cc: [email protected]
> Subject: Re: [OpenGarages] Will Superposition of error flags desynchronize a active-transmitter passive-receiver bus??
>
> I don't think it's a problem. The error delimiter is to be 8 bits and
> the interframe space is 3 bits so it seems to me that there will be
> 8+3 = 11 recessive bits minimum at the end of an error frame. That
> ought to be plenty of bits to get everyone on the same page before
> another frame tries to come through.
> On Mon, Aug 20, 2018 at 3:02 PM Christiano SA <[email protected]> wrote:
> >
> > Imagine the following situation:
> >
> > You have a bus with two nodes:
> > node 1 = transmitter, active-error-node
> > node 2 = receiver, passive-error-node
> >
> > Now an error happens at node 1. As it is a active node, it will transmit 6 dominant bits, but... lets suppose that the third bit generate an error in the node2.
> >
> > The ISO 11898-1:2015, in the page 35 says:
> >
> > """""""""""""""""""""""""""""""""""""""
> > Passive error flags initiated by receivers shall not be able to prevail over any activity on the bus.
> > Therefore, error-passive receivers shall always wait for 6 subsequent equal bits after detecting an error condition.
> > The passive error flag is complete when these 6 equals bits have been detected.
> > """""""""""""""""""""""""""""""""""""""
> >
> > So, from node2's view, it will have to wait 3 (6 total - past 3) dominant bits + 6 recessive bits to follow the rule "6 equal subsequent bits". At the end, node2 can enter in the "error delimiter".
> > However, from the node1's view, it is remaining only 3 bits to enter in the "error delimiter".
> >
> > Isn't it happening desynchrony here?
> >
> > This question is being sended to 2 mailing lists:
> > Canlist
> > Opengarage group
> >
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