RE: Question about CAN Controller bit timing logic

"Liu, Jianye" <[email protected]> Mon, 10 Feb 2020 20:11:09 +0000
Newsgroups gmane.comp.hardware.bus.can
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Hi Ryan,

Thanks for your answer!

I understood the two type of synchronization and checked some documents bel=
ow, but I am more interested about hardware architecture of synchronization=
 part which not included in these documents and website. Could you give me =
more details about the actually hardware architecture in bit timing logic p=
art?

Best Regards,

Rocky Leo
From: Ryan Pannell<mailto:[email protected]>
Sent: Monday, February 10, 2020 12:13 PM
To: [email protected]<mailto:[email protected]=
e>; [email protected]<mailto:[email protected]>
Subject: [CANLIST] RE: Question about CAN Controller bit timing logic

Hi Rocky,

>> I am interested in hardware part about CAN Controller Data
>> Synchronization, so could you tell me how does the Bit Time Logic
>> detect the phase difference and convert the phase difference into
>> exact number of TQs(Time Quanta) to help CAN controller synchronize
>> the Data?

There are 2 types of synchronisation =96 hard synchronisation and re-synchr=
onisation.
Hard synchronisation is performed at the start of frame, when the start of =
frame bit goes from recessive to dominant state.
It is subsequently re-synchronised when a bit changes from recessive to dom=
inant state outside the synchronisation segment, at which point the control=
ler will adjust the segment length to compensate.

Within the controller, synchronisation is usually handled by a DPLL, which =
basically compares the actual position of a bit edge to the expected edge a=
nd adjust the bit time as necessary.

There are a few documents that go into the topic in more detail, such as:

  *   Bosch CAN Specification Version 2.0
  *   ISO 11898
  *   NXP AN1798
  *   Microchip AN754
  *   Kvaser have several PDFs and even videos, I believe
  *   Google is your friend

I hope this helps.

Best,
Ryan


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<p class=3D"MsoNormal">Hi Ryan,</p>
<p class=3D"MsoNormal"><o:p>&nbsp;</o:p></p>
<p class=3D"MsoNormal">Thanks for your answer!</p>
<p class=3D"MsoNormal"><o:p>&nbsp;</o:p></p>
<p class=3D"MsoNormal">I understood the two type of synchronization and che=
cked some documents below, but I am more interested about hardware architec=
ture of synchronization part which not included in these documents and webs=
ite. Could you give me more details
 about the actually hardware architecture in bit timing logic part?</p>
<p class=3D"MsoNormal"><o:p>&nbsp;</o:p></p>
<p class=3D"MsoNormal">Best Regards,</p>
<p class=3D"MsoNormal"><o:p>&nbsp;</o:p></p>
<p class=3D"MsoNormal">Rocky Leo</p>
<div style=3D"mso-element:para-border-div;border:none;border-top:solid #E1E=
1E1 1.0pt;padding:3.0pt 0in 0in 0in">
<p class=3D"MsoNormal" style=3D"border:none;padding:0in"><b>From: </b><a hr=
ef=3D"mailto:[email protected]">Ryan Pannell</a><br>
<b>Sent: </b>Monday, February 10, 2020 12:13 PM<br>
<b>To: </b><a href=3D"mailto:[email protected]">canlist_NOT@=
vector-informatik.de</a>;
<a href=3D"mailto:[email protected]">[email protected]=
e</a><br>
<b>Subject: </b>[CANLIST] RE: Question about CAN Controller bit timing logi=
c</p>
</div>
<p class=3D"MsoNormal"><o:p>&nbsp;</o:p></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">Hi Rocky,<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US"><o:p>&nbsp;</o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">&gt;&gt; </span>
I am interested in hardware part about CAN Controller Data <o:p></o:p></p>
<p class=3D"MsoNormal">&gt;&gt;&nbsp;Synchronization, so could you tell me =
how does the Bit Time Logic
<br>
&gt;&gt; detect the phase difference and convert the phase difference into =
<br>
&gt;&gt; exact number of TQs(Time Quanta) to help CAN controller synchroniz=
e <br>
&gt;&gt; the Data?<o:p></o:p></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US"><o:p>&nbsp;</o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">There are 2 types of synchronisation =96 hard synchronisation and re-=
synchronisation.<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">Hard synchronisation is performed at the start of frame, when the sta=
rt of frame bit goes from recessive to dominant state.<o:p></o:p></span></p=
>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">It is subsequently re-synchronised when a bit changes from recessive =
to dominant state outside the synchronisation segment, at which point the c=
ontroller will adjust the segment length
 to compensate.<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US"><o:p>&nbsp;</o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">Within the controller, synchronisation is usually handled by a DPLL, =
which basically compares the actual position of a bit edge to the expected =
edge and adjust the bit time as necessary.<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US"><o:p>&nbsp;</o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">There are a few documents that go into the topic in more detail, such=
 as:<o:p></o:p></span></p>
<ul style=3D"margin-top:0in" type=3D"disc">
<li class=3D"MsoListParagraph" style=3D"margin-left:0in;mso-list:l0 level1 =
lfo1"><span lang=3D"EN-GB" style=3D"mso-fareast-language:EN-US">Bosch CAN S=
pecification Version 2.0<o:p></o:p></span></li><li class=3D"MsoListParagrap=
h" style=3D"margin-left:0in;mso-list:l0 level1 lfo1"><span lang=3D"EN-GB" s=
tyle=3D"mso-fareast-language:EN-US">ISO 11898<o:p></o:p></span></li><li cla=
ss=3D"MsoListParagraph" style=3D"margin-left:0in;mso-list:l0 level1 lfo1"><=
span lang=3D"EN-GB" style=3D"mso-fareast-language:EN-US">NXP AN1798<o:p></o=
:p></span></li><li class=3D"MsoListParagraph" style=3D"margin-left:0in;mso-=
list:l0 level1 lfo1"><span lang=3D"EN-GB" style=3D"mso-fareast-language:EN-=
US">Microchip AN754<o:p></o:p></span></li><li class=3D"MsoListParagraph" st=
yle=3D"margin-left:0in;mso-list:l0 level1 lfo1"><span lang=3D"EN-GB" style=
=3D"mso-fareast-language:EN-US">Kvaser have several PDFs and even videos, I=
 believe<o:p></o:p></span></li><li class=3D"MsoListParagraph" style=3D"marg=
in-left:0in;mso-list:l0 level1 lfo1"><span lang=3D"EN-GB" style=3D"mso-fare=
ast-language:EN-US">Google is your friend<o:p></o:p></span></li></ul>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US"><o:p>&nbsp;</o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">I hope this helps.<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US"><o:p>&nbsp;</o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">Best,<o:p></o:p></span></p>
<p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"mso-fareast-language:E=
N-US">Ryan<o:p></o:p></span></p>
<p class=3D"MsoNormal"><o:p>&nbsp;</o:p></p>
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