Re: Question about CAN Controller bit timing logic
Ryan Pannell <[email protected]> Mon, 10 Feb 2020 20:27:17 +0000
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--_000_DB8P189MB1080CECE1CF226FA4C6105B8A2190DB8P189MB1080EURP_ Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Hi Rocky, The hardware architecture you mention is actually more a digital logic arch= itecture. You can synthesise this in VHDL or even on a microcontroller with C. Effectively it is a digital phase locked loop. I'm not going to go into lap= lace transforms and deriving equations for this, but there are plenty of re= sources that can explain the math behind this. Simply search "phase locked = loop" . You know the trigger points for the timing from the prior email and= the documents I mentioned, you just need to apply these to the math for a = phase locked loop. Once you understand PLL's you should be able to synthesise this in VHDL or = write a C program to acheive it. Best, Ryan Get Outlook for Android<https://aka.ms/ghei36> ________________________________ From: [email protected] <canlist-owner@vector-informatik.= com> on behalf of Liu, Jianye <[email protected]> Sent: Monday, February 10, 2020 8:11:09 PM To: [email protected] <[email protected]> Subject: [CANLIST] RE: Question about CAN Controller bit timing logic Hi Ryan, Thanks for your answer! I understood the two type of synchronization and checked some documents bel= ow, but I am more interested about hardware architecture of synchronization= part which not included in these documents and website. Could you give me = more details about the actually hardware architecture in bit timing logic p= art? Best Regards, Rocky Leo From: Ryan Pannell<mailto:[email protected]> Sent: Monday, February 10, 2020 12:13 PM To: [email protected]<mailto:[email protected]= e>; [email protected]<mailto:[email protected]> Subject: [CANLIST] RE: Question about CAN Controller bit timing logic Hi Rocky, >> I am interested in hardware part about CAN Controller Data >> Synchronization, so could you tell me how does the Bit Time Logic >> detect the phase difference and convert the phase difference into >> exact number of TQs(Time Quanta) to help CAN controller synchronize >> the Data? There are 2 types of synchronisation =96 hard synchronisation and re-synchr= onisation. Hard synchronisation is performed at the start of frame, when the start of = frame bit goes from recessive to dominant state. It is subsequently re-synchronised when a bit changes from recessive to dom= inant state outside the synchronisation segment, at which point the control= ler will adjust the segment length to compensate. Within the controller, synchronisation is usually handled by a DPLL, which = basically compares the actual position of a bit edge to the expected edge a= nd adjust the bit time as necessary. There are a few documents that go into the topic in more detail, such as: * Bosch CAN Specification Version 2.0 * ISO 11898 * NXP AN1798 * Microchip AN754 * Kvaser have several PDFs and even videos, I believe * Google is your friend I hope this helps. Best, Ryan --_000_DB8P189MB1080CECE1CF226FA4C6105B8A2190DB8P189MB1080EURP_ Content-Type: text/html; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable <html> <head> <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3DWindows-1= 252"> <meta content=3D"text/html; charset=3DWindows-1252"> <meta name=3D"Generator" content=3D"Microsoft Word 15 (filtered medium)"> <style> <!-- @font-face {font-family:Wingdings} @font-face {font-family:"Cambria Math"} @font-face {font-family:DengXian} @font-face {font-family:Calibri} @font-face {} p.MsoNormal, li.MsoNormal, div.MsoNormal {margin:0in; margin-bottom:.0001pt; font-size:11.0pt; font-family:"Calibri",sans-serif} a:link, span.MsoHyperlink {color:blue; text-decoration:underline} p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph {margin-top:0in; margin-right:0in; margin-bottom:0in; margin-left:.5in; margin-bottom:.0001pt; font-size:11.0pt; font-family:"Calibri",sans-serif} .MsoChpDefault {} @page WordSection1 {margin:1.0in 1.0in 1.0in 1.0in} div.WordSection1 {} ol {margin-bottom:0in} ul {margin-bottom:0in} --> </style> </head> <body lang=3D"EN-US" link=3D"blue" vlink=3D"#954F72"> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> Hi Rocky,<br> <br> </div> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> The hardware architecture you mention is actually more a digital logic arch= itecture.<br> </div> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> You can synthesise this in VHDL or even on a microcontroller with C. <br> </div> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> Effectively it is a digital phase locked loop. I'm not going to go into lap= lace transforms and deriving equations for this, but there are plenty of re= sources that can explain the math behind this. Simply search "phase lo= cked loop" . You know the trigger points for the timing from the prior email and the documents I mentioned, you jus= t need to apply these to the math for a phase locked loop.<br> </div> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> Once you understand PLL's you should be able to synthesise this in VHDL or = write a C program to acheive it. <br> <br> </div> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> Best,<br> </div> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> Ryan<br> <br> </div> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> <span id=3D"OutlookSignature"> <div dir=3D"auto" style=3D"direction:ltr; margin:0; padding:0; font-family:= sans-serif; font-size:11pt; color:black"> Get <a href=3D"https://aka.ms/ghei36">Outlook for Android</a></div> </span><br> </div> <hr tabindex=3D"-1" style=3D"display:inline-block; width:98%"> <div id=3D"divRplyFwdMsg" dir=3D"ltr"><font face=3D"Calibri, sans-serif" co= lor=3D"#000000" style=3D"font-size:11pt"><b>From:</b> canlist-owner@vector-= informatik.com <[email protected]> on behalf of Liu= , Jianye <[email protected]><br> <b>Sent:</b> Monday, February 10, 2020 8:11:09 PM<br> <b>To:</b> [email protected] <[email protected]>= ;<br> <b>Subject:</b> [CANLIST] RE: Question about CAN Controller bit timing logi= c</font> <div> </div> </div> <div> <div class=3D"WordSection1"> <p class=3D"MsoNormal">Hi Ryan,</p> <p class=3D"MsoNormal"> </p> <p class=3D"MsoNormal">Thanks for your answer!</p> <p class=3D"MsoNormal"> </p> <p class=3D"MsoNormal">I understood the two type of synchronization and che= cked some documents below, but I am more interested about hardware architec= ture of synchronization part which not included in these documents and webs= ite. Could you give me more details about the actually hardware architecture in bit timing logic part?</p> <p class=3D"MsoNormal"> </p> <p class=3D"MsoNormal">Best Regards,</p> <p class=3D"MsoNormal"> </p> <p class=3D"MsoNormal">Rocky Leo</p> <div style=3D"border:none; border-top:solid #E1E1E1 1.0pt; padding:3.0pt 0i= n 0in 0in"> <p class=3D"MsoNormal" style=3D"border:none; padding:0in"><b>From: </b><a h= ref=3D"mailto:[email protected]">Ryan Pannell</a><br> <b>Sent: </b>Monday, February 10, 2020 12:13 PM<br> <b>To: </b><a href=3D"mailto:[email protected]">canlist_NOT@= vector-informatik.de</a>; <a href=3D"mailto:[email protected]">[email protected]= e</a><br> <b>Subject: </b>[CANLIST] RE: Question about CAN Controller bit timing logi= c</p> </div> <p class=3D"MsoNormal"> </p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">Hi Rocky,</span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D""> </span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">>> </span>I am= interested in hardware part about CAN Controller Data </p> <p class=3D"MsoNormal">>> Synchronization, so could you tell me = how does the Bit Time Logic <br> >> detect the phase difference and convert the phase difference into = <br> >> exact number of TQs(Time Quanta) to help CAN controller synchroniz= e <br> >> the Data?</p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D""> </span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">There are 2 types of= synchronisation =96 hard synchronisation and re-synchronisation.</span></p= > <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">Hard synchronisation= is performed at the start of frame, when the start of frame bit goes from = recessive to dominant state.</span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">It is subsequently r= e-synchronised when a bit changes from recessive to dominant state outside = the synchronisation segment, at which point the controller will adjust the = segment length to compensate.</span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D""> </span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">Within the controlle= r, synchronisation is usually handled by a DPLL, which basically compares t= he actual position of a bit edge to the expected edge and adjust the bit ti= me as necessary.</span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D""> </span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">There are a few docu= ments that go into the topic in more detail, such as:</span></p> <ul type=3D"disc" style=3D"margin-top:0in"> <li class=3D"MsoListParagraph" style=3D"margin-left:0in"><span lang=3D"EN-G= B" style=3D"">Bosch CAN Specification Version 2.0</span></li><li class=3D"M= soListParagraph" style=3D"margin-left:0in"><span lang=3D"EN-GB" style=3D"">= ISO 11898</span></li><li class=3D"MsoListParagraph" style=3D"margin-left:0i= n"><span lang=3D"EN-GB" style=3D"">NXP AN1798</span></li><li class=3D"MsoLi= stParagraph" style=3D"margin-left:0in"><span lang=3D"EN-GB" style=3D"">Micr= ochip AN754</span></li><li class=3D"MsoListParagraph" style=3D"margin-left:= 0in"><span lang=3D"EN-GB" style=3D"">Kvaser have several PDFs and even vide= os, I believe</span></li><li class=3D"MsoListParagraph" style=3D"margin-lef= t:0in"><span lang=3D"EN-GB" style=3D"">Google is your friend</span></li></u= l> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D""> </span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">I hope this helps.</= span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D""> </span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">Best,</span></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB" style=3D"">Ryan</span></p> <p class=3D"MsoNormal"> </p> </div> </div> </body> </html> --_000_DB8P189MB1080CECE1CF226FA4C6105B8A2190DB8P189MB1080EURP_-- -- Archives and useful links: http://groups.yahoo.com/group/CANbus Subscribe and unsubscribe at www.vector.com/canlist/ Report any problems to <[email protected]>