RE: Question about CAN Controller bit timing logic
"Liu, Jianye" <[email protected]> Mon, 10 Feb 2020 21:29:08 +0000
| Newsgroups | gmane.comp.hardware.bus.can |
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--_004_SN6PR02MB5503C09A812925C0C5B87EB790190SN6PR02MB5503namp_ Content-Type: multipart/alternative; boundary="_000_SN6PR02MB5503C09A812925C0C5B87EB790190SN6PR02MB5503namp_" --_000_SN6PR02MB5503C09A812925C0C5B87EB790190SN6PR02MB5503namp_ Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Hi Ryan, Thanks for your answer! Now I am clear about the time synchronization logic and PLL to generate the= clock signal. One thing I still don=92t understand is that how does the ph= ase detector detect the phase difference and convert the phase difference i= nto number of TQs(Time Quantum)? What is the architecture of the phase det= ector? Best Regards, Rocky Leo From: Ryan Pannell<mailto:[email protected]> Sent: Monday, February 10, 2020 2:27 PM To: [email protected]<mailto:[email protected]>; canl= [email protected]<mailto:[email protected]> Subject: [CANLIST] Re: Question about CAN Controller bit timing logic Hi Rocky, The hardware architecture you mention is actually more a digital logic arch= itecture. You can synthesise this in VHDL or even on a microcontroller with C. Effectively it is a digital phase locked loop. I'm not going to go into lap= lace transforms and deriving equations for this, but there are plenty of re= sources that can explain the math behind this. Simply search "phase locked = loop" . You know the trigger points for the timing from the prior email and= the documents I mentioned, you just need to apply these to the math for a = phase locked loop. Once you understand PLL's you should be able to synthesise this in VHDL or = write a C program to acheive it. Best, Ryan Get Outlook for Android<https://aka.ms/ghei36> From: [email protected] <canlist-owner@vector-informatik.= com> on behalf of Liu, Jianye <[email protected]> Sent: Monday, February 10, 2020 8:11:09 PM To: [email protected] <[email protected]> Subject: [CANLIST] RE: Question about CAN Controller bit timing logic Hi Ryan, Thanks for your answer! I understood the two type of synchronization and checked some documents bel= ow, but I am more interested about hardware architecture of synchronization= part which not included in these documents and website. Could you give me = more details about the actually hardware architecture in bit timing logic p= art? Best Regards, Rocky Leo From: Ryan Pannell<mailto:[email protected]> Sent: Monday, February 10, 2020 12:13 PM To: [email protected]<mailto:[email protected]= e>; [email protected]<mailto:[email protected]> Subject: [CANLIST] RE: Question about CAN Controller bit timing logic Hi Rocky, >> I am interested in hardware part about CAN Controller Data >> Synchronization, so could you tell me how does the Bit Time Logic >> detect the phase difference and convert the phase difference into >> exact number of TQs(Time Quanta) to help CAN controller synchronize >> the Data? There are 2 types of synchronisation =96 hard synchronisation and re-synchr= onisation. Hard synchronisation is performed at the start of frame, when the start of = frame bit goes from recessive to dominant state. It is subsequently re-synchronised when a bit changes from recessive to dom= inant state outside the synchronisation segment, at which point the control= ler will adjust the segment length to compensate. Within the controller, synchronisation is usually handled by a DPLL, which = basically compares the actual position of a bit edge to the expected edge a= nd adjust the bit time as necessary. There are a few documents that go into the topic in more detail, such as: * Bosch CAN Specification Version 2.0 * ISO 11898 * NXP AN1798 * Microchip AN754 * Kvaser have several PDFs and even videos, I believe * Google is your friend I hope this helps. Best, Ryan --_000_SN6PR02MB5503C09A812925C0C5B87EB790190SN6PR02MB5503namp_ Content-Type: text/html; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable <html xmlns:v=3D"urn:schemas-microsoft-com:vml" xmlns:o=3D"urn:schemas-micr= osoft-com:office:office" xmlns:w=3D"urn:schemas-microsoft-com:office:word" = xmlns:m=3D"http://schemas.microsoft.com/office/2004/12/omml" xmlns=3D"http:= //www.w3.org/TR/REC-html40"> <head> <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3DWindows-1= 252"> <meta name=3D"Generator" content=3D"Microsoft Word 15 (filtered medium)"> <!--[if !mso]><style>v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style><![endif]--><style><!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4;} @font-face {font-family:DengXian; panose-1:2 1 6 0 3 1 1 1 1 1;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4;} @font-face {font-family:"\@DengXian"; panose-1:2 1 6 0 3 1 1 1 1 1;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {margin:0in; margin-bottom:.0001pt; font-size:11.0pt; font-family:"Calibri",sans-serif;} a:link, span.MsoHyperlink {mso-style-priority:99; color:blue; text-decoration:underline;} p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph {mso-style-priority:34; margin-top:0in; margin-right:0in; margin-bottom:0in; margin-left:.5in; margin-bottom:.0001pt; font-size:11.0pt; font-family:"Calibri",sans-serif;} .MsoChpDefault {mso-style-type:export-only;} @page WordSection1 {size:8.5in 11.0in; margin:1.0in 1.0in 1.0in 1.0in;} div.WordSection1 {page:WordSection1;} /* List Definitions */ @list l0 {mso-list-id:650257796; mso-list-template-ids:-1;} @list l0:level1 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:.5in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level2 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:1.0in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level3 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:1.5in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level4 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:2.0in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level5 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:2.5in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level6 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:3.0in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level7 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:3.5in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level8 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:4.0in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} @list l0:level9 {mso-level-number-format:bullet; mso-level-text:\F0B7; mso-level-tab-stop:4.5in; mso-level-number-position:left; text-indent:-.25in; mso-ansi-font-size:10.0pt; font-family:Symbol;} ol {margin-bottom:0in;} ul {margin-bottom:0in;} --></style> </head> <body lang=3D"EN-US" link=3D"blue" vlink=3D"#954F72"> <div class=3D"WordSection1"> <p class=3D"MsoNormal">Hi Ryan,</p> <p class=3D"MsoNormal"><o:p> </o:p></p> <p class=3D"MsoNormal">Thanks for your answer!</p> <p class=3D"MsoNormal"><o:p> </o:p></p> <p class=3D"MsoNormal">Now I am clear about the time synchronization logic = and PLL to generate the clock signal. One thing I still don=92t understand = is that how does the phase detector detect the phase difference and convert= the phase difference into number of TQs(Time Quantum)? What is the architecture of the phase detector?</= p> <p class=3D"MsoNormal"><o:p> </o:p></p> <p class=3D"MsoNormal">Best Regards,</p> <p class=3D"MsoNormal"><o:p> </o:p></p> <p class=3D"MsoNormal">Rocky Leo<o:p></o:p></p> <div style=3D"mso-element:para-border-div;border:none;border-top:solid #E1E= 1E1 1.0pt;padding:3.0pt 0in 0in 0in"> <p class=3D"MsoNormal" style=3D"border:none;padding:0in"><b>From: </b><a hr= ef=3D"mailto:[email protected]">Ryan Pannell</a><br> <b>Sent: </b>Monday, February 10, 2020 2:27 PM<br> <b>To: </b><a href=3D"mailto:[email protected]">canlist@vector-i= nformatik.de</a>; <a href=3D"mailto:[email protected]">canlist_not@vector-info= rmatik.de</a><br> <b>Subject: </b>[CANLIST] Re: Question about CAN Controller bit timing logi= c</p> </div> <p class=3D"MsoNormal"><o:p> </o:p></p> <p class=3D"MsoNormal" style=3D"margin-bottom:12.0pt"><span style=3D"font-f= amily:"Arial",sans-serif;color:black">Hi Rocky,<o:p></o:p></span>= </p> <div> <p class=3D"MsoNormal"><span style=3D"font-family:"Arial",sans-se= rif;color:black">The hardware architecture you mention is actually more a d= igital logic architecture.<o:p></o:p></span></p> </div> <div> <p class=3D"MsoNormal"><span style=3D"font-family:"Arial",sans-se= rif;color:black">You can synthesise this in VHDL or even on a microcontroll= er with C. <o:p></o:p></span></p> </div> <div> <p class=3D"MsoNormal"><span style=3D"font-family:"Arial",sans-se= rif;color:black">Effectively it is a digital phase locked loop. I'm not goi= ng to go into laplace transforms and deriving equations for this, but there= are plenty of resources that can explain the math behind this. Simply search "phase locked loop" . You know t= he trigger points for the timing from the prior email and the documents I m= entioned, you just need to apply these to the math for a phase locked loop.= <o:p></o:p></span></p> </div> <div> <p class=3D"MsoNormal" style=3D"margin-bottom:12.0pt"><span style=3D"font-f= amily:"Arial",sans-serif;color:black">Once you understand PLL's y= ou should be able to synthesise this in VHDL or write a C program to acheiv= e it. <o:p></o:p></span></p> </div> <div> <p class=3D"MsoNormal"><span style=3D"font-family:"Arial",sans-se= rif;color:black">Best,<o:p></o:p></span></p> </div> <div> <p class=3D"MsoNormal" style=3D"margin-bottom:12.0pt"><span style=3D"font-f= amily:"Arial",sans-serif;color:black">Ryan<o:p></o:p></span></p> </div> <div> <div> <p class=3D"MsoNormal"><span style=3D"font-family:"Arial",sans-se= rif;color:black">Get </span><a href=3D"https://aka.ms/ghei36"><span style=3D"font-family:"A= rial",sans-serif">Outlook for Android</span></a><span style=3D"font-fa= mily:"Arial",sans-serif;color:black"><o:p></o:p></span></p> </div> <p class=3D"MsoNormal"><span style=3D"font-family:"Arial",sans-se= rif;color:black"><o:p> </o:p></span></p> </div> <p class=3D"MsoNormal"><img border=3D"0" width=3D"705" height=3D"1" style= =3D"width:7.3437in;height:.0104in" id=3D"Horizontal_x0020_Line_x0020_1" src= =3D"cid:[email protected]"><o:p></o:p></p> <div id=3D"divRplyFwdMsg"> <p class=3D"MsoNormal"><b><span style=3D"color:black">From:</span></b><span= style=3D"color:black"> [email protected] <canlist-own= [email protected]> on behalf of Liu, Jianye <[email protected].= edu><br> <b>Sent:</b> Monday, February 10, 2020 8:11:09 PM<br> <b>To:</b> [email protected] <[email protected]>= ;<br> <b>Subject:</b> [CANLIST] RE: Question about CAN Controller bit timing logi= c</span> <o:p></o:p></p> <div> <p class=3D"MsoNormal"> <o:p></o:p></p> </div> </div> <div> <div> <p class=3D"MsoNormal">Hi Ryan,<o:p></o:p></p> <p class=3D"MsoNormal"> <o:p></o:p></p> <p class=3D"MsoNormal">Thanks for your answer!<o:p></o:p></p> <p class=3D"MsoNormal"> <o:p></o:p></p> <p class=3D"MsoNormal">I understood the two type of synchronization and che= cked some documents below, but I am more interested about hardware architec= ture of synchronization part which not included in these documents and webs= ite. Could you give me more details about the actually hardware architecture in bit timing logic part?<o:p></o= :p></p> <p class=3D"MsoNormal"> <o:p></o:p></p> <p class=3D"MsoNormal">Best Regards,<o:p></o:p></p> <p class=3D"MsoNormal"> <o:p></o:p></p> <p class=3D"MsoNormal">Rocky Leo<o:p></o:p></p> <div style=3D"border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in = 0in 0in"> <p class=3D"MsoNormal"><b>From: </b><a href=3D"mailto:[email protected]">Ryan = Pannell</a><br> <b>Sent: </b>Monday, February 10, 2020 12:13 PM<br> <b>To: </b><a href=3D"mailto:[email protected]">canlist_NOT@= vector-informatik.de</a>; <a href=3D"mailto:[email protected]">[email protected]= e</a><br> <b>Subject: </b>[CANLIST] RE: Question about CAN Controller bit timing logi= c<o:p></o:p></p> </div> <p class=3D"MsoNormal"> <o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">Hi Rocky,</span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB"> </span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">>> </span>I am interested= in hardware part about CAN Controller Data <o:p></o:p></p> <p class=3D"MsoNormal">>> Synchronization, so could you tell me = how does the Bit Time Logic <br> >> detect the phase difference and convert the phase difference into = <br> >> exact number of TQs(Time Quanta) to help CAN controller synchroniz= e <br> >> the Data?<o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB"> </span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">There are 2 types of synchronis= ation =96 hard synchronisation and re-synchronisation.</span><o:p></o:p></p= > <p class=3D"MsoNormal"><span lang=3D"EN-GB">Hard synchronisation is perform= ed at the start of frame, when the start of frame bit goes from recessive t= o dominant state.</span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">It is subsequently re-synchroni= sed when a bit changes from recessive to dominant state outside the synchro= nisation segment, at which point the controller will adjust the segment len= gth to compensate.</span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB"> </span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">Within the controller, synchron= isation is usually handled by a DPLL, which basically compares the actual p= osition of a bit edge to the expected edge and adjust the bit time as neces= sary.</span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB"> </span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">There are a few documents that = go into the topic in more detail, such as:</span><o:p></o:p></p> <ul style=3D"margin-top:0in" type=3D"disc"> <li class=3D"MsoListParagraph" style=3D"margin-left:0in;mso-list:l0 level1 = lfo1"><span lang=3D"EN-GB">Bosch CAN Specification Version 2.0</span><o:p><= /o:p></li><li class=3D"MsoListParagraph" style=3D"margin-left:0in;mso-list:= l0 level1 lfo1"><span lang=3D"EN-GB">ISO 11898</span><o:p></o:p></li><li cl= ass=3D"MsoListParagraph" style=3D"margin-left:0in;mso-list:l0 level1 lfo1">= <span lang=3D"EN-GB">NXP AN1798</span><o:p></o:p></li><li class=3D"MsoListP= aragraph" style=3D"margin-left:0in;mso-list:l0 level1 lfo1"><span lang=3D"E= N-GB">Microchip AN754</span><o:p></o:p></li><li class=3D"MsoListParagraph" = style=3D"margin-left:0in;mso-list:l0 level1 lfo1"><span lang=3D"EN-GB">Kvas= er have several PDFs and even videos, I believe</span><o:p></o:p></li><li c= lass=3D"MsoListParagraph" style=3D"margin-left:0in;mso-list:l0 level1 lfo1"= ><span lang=3D"EN-GB">Google is your friend</span><o:p></o:p></li></ul> <p class=3D"MsoNormal"><span lang=3D"EN-GB"> </span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">I hope this helps.</span><o:p><= /o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB"> </span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">Best,</span><o:p></o:p></p> <p class=3D"MsoNormal"><span lang=3D"EN-GB">Ryan</span><o:p></o:p></p> </div> </div> <p class=3D"MsoNormal"> <o:p></o:p></p> <p class=3D"MsoNormal"><o:p> </o:p></p> </div> </body> </html> --_000_SN6PR02MB5503C09A812925C0C5B87EB790190SN6PR02MB5503namp_-- --_004_SN6PR02MB5503C09A812925C0C5B87EB790190SN6PR02MB5503namp_ Content-Type: image/png; name="71CBDC2B4BA84781ADAF91ADE1401BE4.png" Content-Description: 71CBDC2B4BA84781ADAF91ADE1401BE4.png Content-Disposition: inline; filename="71CBDC2B4BA84781ADAF91ADE1401BE4.png"; size=135; creation-date="Mon, 10 Feb 2020 21:29:08 GMT"; modification-date="Mon, 10 Feb 2020 21:29:08 GMT" Content-ID: <[email protected]> Content-Transfer-Encoding: base64 iVBORw0KGgoAAAANSUhEUgAAAsEAAAABCAYAAAA/xnPpAAAAAXNSR0IArs4c6QAAAARnQU1BAACx jwv8YQUAAAAJcEhZcwAADsMAAA7DAcdvqGQAAAAcSURBVEhL7cMBDQAADAIg+5f29jhsZKqqqn+m BwZKvl5CiOnJAAAAAElFTkSuQmCC --_004_SN6PR02MB5503C09A812925C0C5B87EB790190SN6PR02MB5503namp_-- -- Archives and useful links: http://groups.yahoo.com/group/CANbus Subscribe and unsubscribe at www.vector.com/canlist/ Report any problems to <[email protected]>